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matchit does not wrap the search for ifndef in Verilog/systemverilog mode

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  • Amol Nagapurkar
    Hi I have following code in verilog/system verilog when i use % key for ifndef else endif keyword it doesn t wrap after reaching endif, where as for all
    Message 1 of 1 , Jun 1 11:40 PM
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      Hi
      I have following code in verilog/system verilog

      when i use "%" key for ifndef else endif keyword it doesn't wrap
      after reaching endif,
      where as for all other keywords it wraps back to start.


      module my_mod
      `ifdef foo
      `else
      `endif

      `ifndef bar
      `else
      `endif

      class
      endclass

      begin
      end

      case
      endcase

      casex
      endcase

      casez
      endcase

      module
      endmodule

      if
      else

      fork
      join

      function
      endfunction

      task
      endtask

      specify
      endspecify

      endmodule

      Please suggest the solution.

      Regards

      Amol N

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