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Opening for Full Time Senior / Principal ASIC Design Engineer

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  • Hongjian Ye
    Hi, We have an opening for full time Senior/Principal ASIC Design Engineer. Here is information about the opening. Please send me your resume if you are
    Message 1 of 1 , Mar 18 1:41 PM
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      Hi,

        We have an opening for full time Senior/Principal ASIC Design Engineer.
      Here is information about the opening. Please send me your resume
      if you are interested.


      Job title

      Senior / Principal Design Engineer   

      Location

      San Jose, California

      Country

      USA

       

       

      Job type

      Full Time, Permanent

      Job description

      Senior / Principal Design Engineer

      Low power micro-architecture design techniques are key design point features of the chips we are developing. High quality, low power and low cost are all key design points for our products. Leading edge process technologies such as 65nm and 40nm.

      Responsibilities: 

      • Developing the micro-architecture of signal processing/data-path blocks
      • Implementing design using industry standard tools including RTL coding using verilog, synthesis, DFT and static timing analysis
      • Working with verification team and backend team to successfully complete chip tape-outs

      Qualifications / Requirements:

      • Masters/Bachelors degree in EE
      • Knowledge of digital signal processing techniques (design and debug)
      • Experience with fixed point design and implementation.
      • Minimum 5 years experience with Verilog ASIC design.
      • Familiar with RTL verification.
      • Experience with low power techniques.
      • Experience with Synthesis and STA tools.

      Hongjian

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