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Urgent , Help needed: Trimedia TM1300 Details

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  • Saket Kumar
    Hi all I am a graduate student at the University of Texas at Austin. I am undertaking a class on Superscalar Microprocessor design and as a part of the course,
    Message 1 of 4 , Sep 30, 2003
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      Hi all
      I am a graduate student at the University of Texas at Austin. I am
      undertaking a class on Superscalar Microprocessor design and as a
      part of the course, I have to give a survey report containing the
      following details for Trimedia processors. I am filling in the
      information that I have managed to gather. I was just wondering if
      someone could help me out in filling the remaining ones. Correct me,
      if I am wrong in the ones that I have filled.
      Thanks in advance,
      -Saket

      Price: US $:
      # transistors :
      Die size:
      # metallization layers:
      Cooling mechanism:
      Copper technology?:
      Average power :
      # pipeline stages :
      Out of order execution? :
      Number of instructions in flight :
      Fetch width :
      Decode width :
      execute width :
      retire width :
      Register renaming? :
      ROB size if any :
      Central Window or reservation station? :
      Does this processor have an embedded SIMD extension? If yes, what is
      the name? : yes (I dont know the name)
      What kind of page table? :
      Branch Predictor type :
      Branch predictor size :



      Processor:TRIMEDIA (I chose TM1300 for the survey)
      Company:Philips
      Clock rate : 166 MHz
      Year of introduction : 1999
      Technology ( feature size) : 0.25u
      Peak Power : 3.5W
      Is this processor Superscalar? : No
      Is this processor VLIW? : Yes
      SPECint rating : Not submitted
      SPECfp rating : Not submitted
      Datapath width (bits): 32
      Instruction width : variable
      Number of registers : 128
      Endian : little or big
      # functional units : 27
      # load/store units : 2
      I-cache: L1 size : 32KB
      L1 associativity : 8
      L1 block size : 64
      L1 latency : 3 cycles for branch delays
      Number of L1 ports : 2
      L2 - unified or split?
      Data Cache L1 size : 16 KB
      L1 associativity :8
      L1 block size : 84
      L1 latency : 3 cycles for both load and store
      Number of L1 ports : 2
      Cache replacement policy : Hierarchical LRU
      Page size : variable from 4 KB to 16 MB
    • alfred@mds.com
      Part of the unstated reason for these exercises is to give you a chance to read about these processors. By getting only the answers to these questions from
      Message 2 of 4 , Oct 1, 2003
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        Part of the unstated reason for these exercises is to give you a chance
        to read about these processors. By getting only the answers to these
        questions from the expert, you are missing that opportunity to learn more about
        these processor, unless of course you have higher priority tasks.

        Best Regards,
        Alfred Lee


        ----- Original Message -----
        From: "Saket Kumar" <saket_uor@...>
        To: <trimedia@yahoogroups.com>
        Sent: Tuesday, September 30, 2003 4:21 PM
        Subject: [trimedia] Urgent , Help needed: Trimedia TM1300 Details


        > Hi all
        > I am a graduate student at the University of Texas at Austin. I am
        > undertaking a class on Superscalar Microprocessor design and as a
        > part of the course, I have to give a survey report containing the
        > following details for Trimedia processors. I am filling in the
        > information that I have managed to gather. I was just wondering if
        > someone could help me out in filling the remaining ones. Correct me,
        > if I am wrong in the ones that I have filled.
        > Thanks in advance,
        > -Saket
        >
        > Price: US $:
        > # transistors :
        > Die size:
        > # metallization layers:
        > Cooling mechanism:
        > Copper technology?:
        > Average power :
        > # pipeline stages :
        > Out of order execution? :
        > Number of instructions in flight :
        > Fetch width :
        > Decode width :
        > execute width :
        > retire width :
        > Register renaming? :
        > ROB size if any :
        > Central Window or reservation station? :
        > Does this processor have an embedded SIMD extension? If yes, what is
        > the name? : yes (I dont know the name)
        > What kind of page table? :
        > Branch Predictor type :
        > Branch predictor size :
        >
        >
        >
        > Processor:TRIMEDIA (I chose TM1300 for the survey)
        > Company:Philips
        > Clock rate : 166 MHz
        > Year of introduction : 1999
        > Technology ( feature size) : 0.25u
        > Peak Power : 3.5W
        > Is this processor Superscalar? : No
        > Is this processor VLIW? : Yes
        > SPECint rating : Not submitted
        > SPECfp rating : Not submitted
        > Datapath width (bits): 32
        > Instruction width : variable
        > Number of registers : 128
        > Endian : little or big
        > # functional units : 27
        > # load/store units : 2
        > I-cache: L1 size : 32KB
        > L1 associativity : 8
        > L1 block size : 64
        > L1 latency : 3 cycles for branch delays
        > Number of L1 ports : 2
        > L2 - unified or split?
        > Data Cache L1 size : 16 KB
        > L1 associativity :8
        > L1 block size : 84
        > L1 latency : 3 cycles for both load and store
        > Number of L1 ports : 2
        > Cache replacement policy : Hierarchical LRU
        > Page size : variable from 4 KB to 16 MB
        >
        >
        >
        >
        > Sent via the TriMedia mailing list
        > trimedia@yahoogroups.com - archive at http://groups.yahoo.com/group/trimedia
        >
        > Your use of Yahoo! Groups is subject to http://docs.yahoo.com/info/terms/
        >
        >
      • Saket Kumar
        Thanks for your response sir. I do know it very well that I need to read about the processor for them and I browsed thro the datasheet(thats what you can do
        Message 3 of 4 , Oct 1, 2003
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          Thanks for your response sir. I do know it very well
          that I need to read about the processor for them and I
          browsed thro the datasheet(thats what you can do for a
          3-days assignment when you are supposed to survey 2
          different processors.) I am not at all interested in
          using Trimedia processors, so I dont think it is
          advisable to go thro the complete datasheet.Moreover,
          I browsed through it and could not get some of the
          microarchitectural details that I mentioned.
          Anyways, thanks for taking your time to give those
          invaluable suggestions.
          -saket

          --- alfred@... wrote:
          > Part of the unstated reason for these exercises is
          > to give you a chance
          > to read about these processors. By getting only the
          > answers to these
          > questions from the expert, you are missing that
          > opportunity to learn more about
          > these processor, unless of course you have higher
          > priority tasks.
          >
          > Best Regards,
          > Alfred Lee
          >
          >
          > ----- Original Message -----
          > From: "Saket Kumar" <saket_uor@...>
          > To: <trimedia@yahoogroups.com>
          > Sent: Tuesday, September 30, 2003 4:21 PM
          > Subject: [trimedia] Urgent , Help needed: Trimedia
          > TM1300 Details
          >
          >
          > > Hi all
          > > I am a graduate student at the University of
          > Texas at Austin. I am
          > > undertaking a class on Superscalar Microprocessor
          > design and as a
          > > part of the course, I have to give a survey report
          > containing the
          > > following details for Trimedia processors. I am
          > filling in the
          > > information that I have managed to gather. I was
          > just wondering if
          > > someone could help me out in filling the remaining
          > ones. Correct me,
          > > if I am wrong in the ones that I have filled.
          > > Thanks in advance,
          > > -Saket
          > >
          > > Price: US $:
          > > # transistors :
          > > Die size:
          > > # metallization layers:
          > > Cooling mechanism:
          > > Copper technology?:
          > > Average power :
          > > # pipeline stages :
          > > Out of order execution? :
          > > Number of instructions in flight :
          > > Fetch width :
          > > Decode width :
          > > execute width :
          > > retire width :
          > > Register renaming? :
          > > ROB size if any :
          > > Central Window or reservation station? :
          > > Does this processor have an embedded SIMD
          > extension? If yes, what is
          > > the name? : yes (I dont know the name)
          > > What kind of page table? :
          > > Branch Predictor type :
          > > Branch predictor size :
          > >
          > >
          > >
          > > Processor:TRIMEDIA (I chose TM1300 for the survey)
          > > Company:Philips
          > > Clock rate : 166 MHz
          > > Year of introduction : 1999
          > > Technology ( feature size) : 0.25u
          > > Peak Power : 3.5W
          > > Is this processor Superscalar? : No
          > > Is this processor VLIW? : Yes
          > > SPECint rating : Not submitted
          > > SPECfp rating : Not submitted
          > > Datapath width (bits): 32
          > > Instruction width : variable
          > > Number of registers : 128
          > > Endian : little or big
          > > # functional units : 27
          > > # load/store units : 2
          > > I-cache: L1 size : 32KB
          > > L1 associativity : 8
          > > L1 block size : 64
          > > L1 latency : 3 cycles for branch delays
          > > Number of L1 ports : 2
          > > L2 - unified or split?
          > > Data Cache L1 size : 16 KB
          > > L1 associativity :8
          > > L1 block size : 84
          > > L1 latency : 3 cycles for both load and store
          > > Number of L1 ports : 2
          > > Cache replacement policy : Hierarchical LRU
          > > Page size : variable from 4 KB to 16 MB
          > >
          > >
          > >
          > >
          > > Sent via the TriMedia mailing list
          > > trimedia@yahoogroups.com - archive at
          > http://groups.yahoo.com/group/trimedia
          > >
          > > Your use of Yahoo! Groups is subject to
          > http://docs.yahoo.com/info/terms/
          > >
          > >
          >


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        • Chris Bore
          Well, some of the detail requested is hidden in the ... This is a microarchitectural issue, so you will have to hope one of the microarchitects responds. The
          Message 4 of 4 , Oct 1, 2003
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            Well, some of the detail requested is hidden in the
            microarchitecture, but here are one or tw of the points clarified:

            > > > # pipeline stages :
            This is a microarchitectural issue, so you will have to hope one of
            the microarchitects responds. The overt pipeline applies in the usage
            of some functional units at the ISA level: each unit has its own
            latency - most have a single cuc=ycle, some (floating point ALUs and
            int/float MULs) have a 3-cycle latency.

            > > > Out of order execution? :
            Yes. There is a degree of fine tunin control over this too, to do
            with relaxing the ways C requires execution.

            > > > Number of instructions in flight :
            > > > Fetch width :
            variable (instructions are compressed in both i-cache and DRAM)

            > > > Decode width :
            > > > execute width :
            224 bits (decompressed on despatch from i-cache)

            > > > retire width :
            > > > Register renaming? :
            No. There are a large number of registers (128) , so alternate
            strategies can be used more efficently.

            > > > ROB size if any :
            > > > Central Window or reservation station? :
            > > > Does this processor have an embedded SIMD
            > > extension? If yes, what is
            Many of the functional units have SIMD operation. These are called
            SIMD or custom operations. There is along list - one of the features
            of TriMedia is its very rich set of SIMD extensions for multimedia.


            Under data cache, you listed block size as 84 - surely a typo, it is
            64.

            Also, you note the d-cache as having two ports - almost, but not
            quite, true. It is pseudo-dual ported (mechanism is to have 8 cache
            banks so many dual loads hit different cache banks - this is not the
            same as dual ported.

            That's all I have time for.

            Chris
            =================================
            Chris Bore
            BORES Signal Processing
            chris@...
            www.bores.com

            > > > the name? : yes (I dont know the name)
            > > > What kind of page table? :
            > > > Branch Predictor type :
            > > > Branch predictor size :
            > > >
            > > >
            > > >
            > > > Processor:TRIMEDIA (I chose TM1300 for the survey)
            > > > Company:Philips
            > > > Clock rate : 166 MHz
            > > > Year of introduction : 1999
            > > > Technology ( feature size) : 0.25u
            > > > Peak Power : 3.5W
            > > > Is this processor Superscalar? : No
            > > > Is this processor VLIW? : Yes
            > > > SPECint rating : Not submitted
            > > > SPECfp rating : Not submitted
            > > > Datapath width (bits): 32
            > > > Instruction width : variable
            > > > Number of registers : 128
            > > > Endian : little or big
            > > > # functional units : 27
            > > > # load/store units : 2
            > > > I-cache: L1 size : 32KB
            > > > L1 associativity : 8
            > > > L1 block size : 64
            > > > L1 latency : 3 cycles for branch delays
            > > > Number of L1 ports : 2
            > > > L2 - unified or split?
            > > > Data Cache L1 size : 16 KB
            > > > L1 associativity :8
            > > > L1 block size : 84
            > > > L1 latency : 3 cycles for both load and store
            > > > Number of L1 ports : 2
            > > > Cache replacement policy : Hierarchical LRU
            > > > Page size : variable from 4 KB to 16 MB
            > > >
            > > >
            > > >
            > > >
            > > > Sent via the TriMedia mailing list
            > > > trimedia@yahoogroups.com - archive at
            > > http://groups.yahoo.com/group/trimedia
            > > >
            > > > Your use of Yahoo! Groups is subject to
            > > http://docs.yahoo.com/info/terms/
            > > >
            > > >
            > >
            >
            >
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