Re: [softrock40] How does the 74AC74 divider circuit work?

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Message 1 of 7 , Jun 16, 2013
Chris,

> ...how the 74AC74 circuit divides the oscillator sigal by 4...
> ...what causes the 2 clock signals to be 90 degrees out of phase...

http://www.norcalqrp.org/files/tayloe_mixer_x3a.pdf

If you want a different presentation on this quadrature detector, you
can find one by Gerald Youngblood. This link points you to the
four-part article called "A Software Defined Radio for the masses".

The Part 1 article, about page 6 starts discussing the specifics of the
74AC74 after a broader introduction to the theory.

73 de Daniel KB3MUN
• The 74AC74 is a logic circuit known as a D Flip-Flop . This is one of several types of flip flops. Flip flops form the basic storage element in digital logic.
Message 2 of 7 , Jun 16, 2013
The 74AC74 is a logic circuit known as a "D Flip-Flop". This is one of several types of flip flops. Flip flops form the basic storage element in digital logic.

The D flip flop has two main inputs called Clock and Data. Data is also referred to as the D input. The output is called Q and there is a secondary output known as /Q or Q' which is logically inverted from Q, meaning that whenever Q is at a high voltage level, /Q will be at a low voltage level and vice versa.

The D flip flop's behavior is very simple. When the clock input switches from a low voltage to a high voltage,  then whatever voltage (low or high) is present on the D input gets captured and appears at the Q output (and inverted at the /Q output).

We say that the flip-flop state is updated at the rising edge of the clock. At all other times, the Q output remains unchanged.

Now, to your question. If you take the /Q output of a D flip flop and connect it to the D input you will observe an interesting result. Imagine that the clock signal is a square wave at frequency F. You will see that this connection results in a signal at Q that is also a square wave but at a frequency of F/2 . Each time the clock square wave rises (goes from a low voltage to a high voltage), the Q output will change from its current state to the opposite of its current state. For example, if we start from the state where the output is low, the first cycle of the clock will make the output high and second cycle of the clock will make the output low again. Thus, to get a single complete cycle on the output, you need two cycle on the clock.

To divide by 4, you connect the Q output of the first flip-flop to the clock input of a second flip flop that is connected in the same fashion from its /Q output back to its D input.  You can form an arbitrarily long divide chain this way and divide by any power of 2 that you wish.

This WIKI goes into various types of flip-flops in detail but requires that you have a basic grasp of digital logic gates:

Maybe somebody else wants to tack the 90 degree question. I think that you need to grasp logic circuit fundamentals to understand that.

TOny

To: softrock40@yahoogroups.com
From: chris_hite@...
Date: Sun, 16 Jun 2013 11:23:20 +0000
Subject: [softrock40] How does the 74AC74 divider circuit work?

I am in the process of building the Ensemble II RX circuit, and am one of thoses guys that likes to understand everything completely. Can anyone explain in more detail how the 74AC74 circuit divides the oscillator sigal by 4. And more importantly, please explain what causes the 2 clock signals to be 90 degrees out of phase. The documentation on the internet seems quite vague on this subject.

Chris

• OK, I guess I should have looked at the schematic before I responded. The description I provided applies exactly to U12 which is only used on the LF version of
Message 3 of 7 , Jun 16, 2013
OK, I guess I should have looked at the schematic before I responded. The description I provided applies exactly to U12 which is only used on the LF version of the RX ensemble II. However, the circuit for U14 is not quite as I described. It manages to create the 90 degree shift and the division by 4 in the same circuit. Given the basic behavior of the D flip flop, this circuit can also be understood fairly readily. In this case both flip flops of U14 receive the same clock signal. To determine what the circuit is going to do, we just need to make a table. Lets start with this:

/Qa     Qb
U14-6   U14-9

low     low    These two outputs are initially both at low voltage.

Now lets apply one rising edge to the clock pin. Given that U14-9 is connected to the D input of U12 flip flop A and it is low when the clock rises, the next state of Qa must be low (and /Qa must then be high).

Similarly, since the D input of U14 flip flop B is connected to U14-6 and it is currently low, then Qb must stay low after a rising edge on the clock.

So, after one rising edge of the clock pin, we end up with /Qa high and Qb low:

/Qa     Qb
U14-6   U14-9

low     low      These two outputs are initially both at low voltage.
high    low      After one rising edge on the clock, /Qa goes high

Following the same analysis, we can fill in the sequence for three more clocks:

/Qa     Qb
U14-6   U14-9

low     low     These two outputs are initially both at low voltage.
high    low     After one rising edge on the clock, /Qa goes high
high    high     then Qb goes high on the next rising edge of the clock
low     high      then /Qa goes low on the next risig edge of the clock
low     low         then we get back to where we started from

Now, lets replace "low" with 0 and "high" with 1 and write out the sequence. Time goes horizontally now
instead of vertically as in the table above.

Clock:  010101010101010101010101010101010101010101010101010101010101... (square wave clock signal)
/Qa     011110000111100001111000011110000111100001111000011110000111... sq wave 1/4 clock freq
Qb     000111100001111000011110000111100001111000011110000111100001... sq wave 1/4 clock freq + 90 deg

For the LF circuit, the output of the first divide by 4 (U12) is the clock for this one (U14).

Hope that helps.

Tony

To: softrock40@yahoogroups.com
From: canthony15@...
Date: Sun, 16 Jun 2013 08:04:22 -0600
Subject: RE: [softrock40] How does the 74AC74 divider circuit work?

The 74AC74 is a logic circuit known as a "D Flip-Flop". This is one of several types of flip flops. Flip flops form the basic storage element in digital logic.

The D flip flop has two main inputs called Clock and Data. Data is also referred to as the D input. The output is called Q and there is a secondary output known as /Q or Q' which is logically inverted from Q, meaning that whenever Q is at a high voltage level, /Q will be at a low voltage level and vice versa.

The D flip flop's behavior is very simple. When the clock input switches from a low voltage to a high voltage,  then whatever voltage (low or high) is present on the D input gets captured and appears at the Q output (and inverted at the /Q output).

We say that the flip-flop state is updated at the rising edge of the clock. At all other times, the Q output remains unchanged.

Now, to your question. If you take the /Q output of a D flip flop and connect it to the D input you will observe an interesting result. Imagine that the clock signal is a square wave at frequency F. You will see that this connection results in a signal at Q that is also a square wave but at a frequency of F/2 . Each time the clock square wave rises (goes from a low voltage to a high voltage), the Q output will change from its current state to the opposite of its current state. For example, if we start from the state where the output is low, the first cycle of the clock will make the output high and second cycle of the clock will make the output low again. Thus, to get a single complete cycle on the output, you need two cycle on the clock.

To divide by 4, you connect the Q output of the first flip-flop to the clock input of a second flip flop that is connected in the same fashion from its /Q output back to its D input.  You can form an arbitrarily long divide chain this way and divide by any power of 2 that you wish.

This WIKI goes into various types of flip-flops in detail but requires that you have a basic grasp of digital logic gates:

Maybe somebody else wants to tack the 90 degree question. I think that you need to grasp logic circuit fundamentals to understand that.

TOny

To: softrock40@yahoogroups.com
From: chris_hite@...
Date: Sun, 16 Jun 2013 11:23:20 +0000
Subject: [softrock40] How does the 74AC74 divider circuit work?

I am in the process of building the Ensemble II RX circuit, and am one of thoses guys that likes to understand everything completely. Can anyone explain in more detail how the 74AC74 circuit divides the oscillator sigal by 4. And more importantly, please explain what causes the 2 clock signals to be 90 degrees out of phase. The documentation on the internet seems quite vague on this subject.

Chris

• Try the file Synchronous Clocks .pdf in the Files section - it is almost at the bottom of the file listings. or
Message 4 of 7 , Jun 16, 2013
Try the file "Synchronous Clocks .pdf" in the Files section - it is almost at the bottom of the file listings.
or

http://f1.grp.yahoofs.com/v1/iBy-UbUCRqGPMA6riF8MsYz9Z0j58yUwGb1e7fzy78Ku-2jioXgBSExhAZoF8ErDAPpypnIGLPKBBDTFZkZMqNEIba4mLhXWNg/Synchronous%20Clocks%20.pdf

Dick K9IVB

--- In softrock40@yahoogroups.com, "ac4fc" <chris_hite@...> wrote:
>
> I am in the process of building the Ensemble II RX circuit, and am one of thoses guys that likes to understand everything completely. Can anyone explain in more detail how the 74AC74 circuit divides the oscillator sigal by 4. And more importantly, please explain what causes the 2 clock signals to be 90 degrees out of phase. The documentation on the internet seems quite vague on this subject.
>
>
> Chris
>
• There is a good diagram of the quadrature clock in the manual for the Softrock Lite II - see http://www.wb5rvz.org/softrock_lite_ii/03_div The Ensemble RXTX
Message 5 of 7 , Jun 16, 2013
There is a good diagram of the quadrature clock in the manual for the Softrock Lite II - see http://www.wb5rvz.org/softrock_lite_ii/03_div  The Ensemble RXTX and the Ensemble II RX (HF version) use the same circuit, but the manual for the Lite shows the quadrature divider all by itself.

On Sun, Jun 16, 2013 at 4:19 PM, dick_faust wrote:

Try the file "Synchronous Clocks .pdf" in the Files section - it is almost at the bottom of the file listings.
or

http://f1.grp.yahoofs.com/v1/iBy-UbUCRqGPMA6riF8MsYz9Z0j58yUwGb1e7fzy78Ku-2jioXgBSExhAZoF8ErDAPpypnIGLPKBBDTFZkZMqNEIba4mLhXWNg/Synchronous%20Clocks%20.pdf

Dick K9IVB

--- In softrock40@yahoogroups.com, "ac4fc" <chris_hite@...> wrote:
>
> I am in the process of building the Ensemble II RX circuit, and am one of thoses guys that likes to understand everything completely. Can anyone explain in more detail how the 74AC74 circuit divides the oscillator sigal by 4. And more importantly, please explain what causes the 2 clock signals to be 90 degrees out of phase. The documentation on the internet seems quite vague on this subject.
>
>
> Chris
>

• Excellent description...thanks to all for the understanding. Chris
Message 6 of 7 , Jun 18, 2013
Excellent description...thanks to all for the understanding.

Chris

--- In softrock40@yahoogroups.com, Anthony Casorso <canthony15@...> wrote:
>
> OK, I guess I should have looked at the schematic before I responded. The description I provided applies exactly to U12 which is only used on the LF version of the RX ensemble II. However, the circuit for U14 is not quite as I described. It manages to create the 90 degree shift and the division by 4 in the same circuit. Given the basic behavior of the D flip flop, this circuit can also be understood fairly readily. In this case both flip flops of U14 receive the same clock signal. To determine what the circuit is going to do, we just need to make a table. Lets start with this:
>
> /Qa Qb
> U14-6 U14-9
> low low These two outputs are initially both at low voltage.
>
> Now lets apply one rising edge to the clock pin. Given that U14-9 is connected to the D input of U12 flip flop A and it is low when the clock rises, the next state of Qa must be low (and /Qa must then be high).
>
> Similarly, since the D input of U14 flip flop B is connected to U14-6 and it is currently low, then Qb must stay low after a rising edge on the clock.
>
> So, after one rising edge of the clock pin, we end up with /Qa high and Qb low:
>
> /Qa Qb
> U14-6 U14-9
> low low These two outputs are initially both at low voltage.
> high low After one rising edge on the clock, /Qa goes high
>
> Following the same analysis, we can fill in the sequence for three more clocks:
>
> /Qa Qb
> U14-6 U14-9
> low low These two outputs are initially both at low voltage.
> high low After one rising edge on the clock, /Qa goes high
> high high then Qb goes high on the next rising edge of the clock
> low high then /Qa goes low on the next risig edge of the clock
> low low then we get back to where we started from
>
> Now, lets replace "low" with 0 and "high" with 1 and write out the sequence. Time goes horizontally now
> instead of vertically as in the table above.
>
> Clock: 010101010101010101010101010101010101010101010101010101010101... (square wave clock signal)
> /Qa 011110000111100001111000011110000111100001111000011110000111... sq wave 1/4 clock freq
> Qb 000111100001111000011110000111100001111000011110000111100001... sq wave 1/4 clock freq + 90 deg
>
> For the LF circuit, the output of the first divide by 4 (U12) is the clock for this one (U14).
>
> Hope that helps.
>
> Tony
> To: softrock40@yahoogroups.com
> From: canthony15@...
> Date: Sun, 16 Jun 2013 08:04:22 -0600
> Subject: RE: [softrock40] How does the 74AC74 divider circuit work?
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> The 74AC74 is a logic circuit known as a "D Flip-Flop". This is one of several types of flip flops. Flip flops form the basic storage element in digital logic.
> The D flip flop has two main inputs called Clock and Data. Data is also referred to as the D input. The output is called Q and there is a secondary output known as /Q or Q' which is logically inverted from Q, meaning that whenever Q is at a high voltage level, /Q will be at a low voltage level and vice versa.
> The D flip flop's behavior is very simple. When the clock input switches from a low voltage to a high voltage, then whatever voltage (low or high) is present on the D input gets captured and appears at the Q output (and inverted at the /Q output).
> We say that the flip-flop state is updated at the rising edge of the clock. At all other times, the Q output remains unchanged.
> Now, to your question. If you take the /Q output of a D flip flop and connect it to the D input you will observe an interesting result. Imagine that the clock signal is a square wave at frequency F. You will see that this connection results in a signal at Q that is also a square wave but at a frequency of F/2 . Each time the clock square wave rises (goes from a low voltage to a high voltage), the Q output will change from its current state to the opposite of its current state. For example, if we start from the state where the output is low, the first cycle of the clock will make the output high and second cycle of the clock will make the output low again. Thus, to get a single complete cycle on the output, you need two cycle on the clock.
>
> To divide by 4, you connect the Q output of the first flip-flop to the clock input of a second flip flop that is connected in the same fashion from its /Q output back to its D input. You can form an arbitrarily long divide chain this way and divide by any power of 2 that you wish.
> This WIKI goes into various types of flip-flops in detail but requires that you have a basic grasp of digital logic gates:
> http://en.wikipedia.org/wiki/Flip-flop_(electronics)
> Maybe somebody else wants to tack the 90 degree question. I think that you need to grasp logic circuit fundamentals to understand that.
> TOny
>
> To: softrock40@yahoogroups.com
> From: chris_hite@...
> Date: Sun, 16 Jun 2013 11:23:20 +0000
> Subject: [softrock40] How does the 74AC74 divider circuit work?
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> I am in the process of building the Ensemble II RX circuit, and am one of thoses guys that likes to understand everything completely. Can anyone explain in more detail how the 74AC74 circuit divides the oscillator sigal by 4. And more importantly, please explain what causes the 2 clock signals to be 90 degrees out of phase. The documentation on the internet seems quite vague on this subject.
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> Chris
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