Re: [softrock40] SDR design considerations
- Hi Andrew,I am new to this list and to the Amateur radio SDR world (I am waiting for a couple softrock kits I just ordered) but I do have some experience in designing and building SDRs for other purposes in my profession. I suggest you have a look at the GNU Radio project and the companion hardware called USRP. The code is open source and the hardware design docs are open source too. Or you can buy prebuilt hardware from Ettus Research although it is pricy. The original USRP uses an Analog Devices ADC/DAC at 64MSps and an FPGA to convert to a USB interface to get the data into a PC. The USRP2 uses ethernet instead of USB to get a higher throughput to the PC.GNU Radio Project: http://www.gnuradio.orgThe documentation for the USRP is available here: http://gnuradio.org/redmine/wiki/1/USRPSchematics for USRP2 and the RF front-end boards are here: http://code.ettus.com/redmine/ettus/projects/public/documentsEttus Research: www.ettus.comTheir design uses a dual ADC/DAC to capture I & Q rather than a single ADC. You may want to go with a dual ADC so you have the flexibility of using IQ sampling if you want to. There are advantages of doing that for some kinds of modulation.I was not involved in that design but I have done a design that was similar although it didn't use a PC. All the processing was done in an FPGA. So have a look at what they did and if you have questions I may be able to help.Russ - VE7VRFOn Sat, Nov 27, 2010 at 12:07 PM, NO one IMPORTANT <foreigner_belt_buckle@...> wrote:
Hello all, I am trying to figure out the best way to make a SDR that uses a dedicated ADC and can sample from about 1Mhz to 30Mhz. My first idea was to make a front-end much like the Softrock 40 with a LO of ~15MHz and sample the I/Q with two 30Ms/s ADC's, but whenever I look at the spectrum input for an DCR there is always a hole in the reception at the LO frequency, is this just part of the way DCR's work or does this have to do with the ADC not responding to the baseband DC? My second was to sample with a single 60MHz ADC. Ether way I believe I will have to use a FPGA to build Ethernet frames as gigabyte Ethernet will likely be the output, so my questions is where can I find a good tutorial or example on how to wire an ADC to a FPGA?
Thank you all!