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Re: Synchronous Clocking mods for V8.0 and older rx

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  • Giancarlo
    ... reciever ... and ... done ... clocking? ... the ... I ... opposite ... db ... it ... change]. ... specified ... Hi all, the problem of not seeing any much
    Message 1 of 4 , Dec 2, 2008
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      --- In softrock40@yahoogroups.com, "dick_faust" <dick_faust@...>
      wrote:
      >
      > --- In softrock40@yahoogroups.com, "danhop7a" <hopperdhh@> wrote:
      > >
      > >
      > > I have removed U5 on a Lite+Xtall v8.0 receiver, cut a couple of
      > > traces, and rewired U6 to be like the V8.3 receiver. The
      reciever
      > > still works(!), but I don't have any data to show how much it
      > helped.
      > >
      > > Would this be a worthwhile modification for older SoftRock RX's
      and
      > > RXTX's? I realize that this could cause lots of grief if not
      done
      > > right! What is the improvement when going to synchronous
      clocking?
      > >
      > > Dan K9WEK
      > >
      > Hi Dan,
      > The synchronus clocks maintain timing relationships at the higher
      > operating frequencies [ie 20M up] where other chip parameters like
      > prop delay, risetime, etc can create significant timing errors.
      >
      > The effect of poor timing is that the percentage of time each of
      the
      > four outputs gets will be less uniform, and this in turn will hurt
      I
      > and Q as they will not be as accurate as they should be, which in
      > turn harms the USB/LSB separation. 10% error gives 20 db of
      opposite
      > side band suppression, 1% gives 40 db, 0.1% gives 60 db, etc. 60
      db
      > is hard to get.
      >
      > Rockey offers a software correction process over time, but I think
      it
      > must recalculate when bands are changed [because the timings
      change].
      >
      > I have a paper in the Files root called Synchronous Clocks.pdf
      > that compares both systems. You would need a fairly powerful
      > simulator to evaluate both timing systems at 120 MHz which would be
      > the maximum clocking frequency for 10 Meters [30MHz x 4] and
      > represent the worst case senario.
      >
      > The original Softrock40 circuit was ok for 80M & 40M because it was
      > operating well below the 74HC74 critical parameters, but not so for
      > higher bands.
      >
      > Using synchronous clocking by itself is a good idea because it
      > minimizes timing errors. But do not neglect to evaluate the
      specified
      > performance of the actual chips at the maximum desired operating
      > frequency.
      >
      > Hope this helps, 73
      >
      > Dick Faust K9IVB

      Hi all,

      the problem of not seeing any much improvement from classic softrock
      to synchronous clock is due to the FST3253. This chip has internal
      decoding so your clock cannot improve much and get worst going up in
      frequency. Some "visible" results can be seen using a digital
      quadrature generatore with divide by 2 (see in File some of my old
      information) as you can "disadjust" the quadrature.

      A possible improvement using synchronous clcok will be seen using the
      FST3125 and 180 degrees phase duration clocks (0, 90, 180, 270).

      73

      Gian
      I7SWX
      >
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