Re: Fw: [softrock40] DDS spurs, was Got my 5.0....Now what do I need?
- Joe,Think about it the dds phase modulation is not stable it jerks around as the dac dumps out samples. Driving a dds into logic gate or comparator to square it up eliminates most of the jerks in the phase noise because it only matters at the logic decision or switch points. Say there is a phase jerk at logic high, nothing is going to change The logic state does not change unless the switch point is crossed..A synthesizer trick is to run at a multiple of the frequency then divide down to the frequency you need. This reduces phase noise and increases resolution. bad comparasion (due to loop filter response) but similar effect.I think the hot set up these days is to use a DDS as a synthesizer reference then run a VCO through a fixed divide by N.If I am crazy please set me straight, I build receivers and use to failure.frank
Joe Rocci <joe@...> wrote:"A dds into dividers like flip flops or a comparator eliminates the effect or spurs over most ot the clock cycle. It only can change the time of the switch slightly. The rest of the cycle is not efected"Francis,How do you explain the above statement? I believe that most of the DDS spurs are phase related, which means that they are manifested as jitter in the zero-crossings of the sine-wave output. Squaring-up the signal in a digital circuit might remove amplitude-related spurious signal components, but I don't see how it can do anything for phase related spurious signal components. Furthermore, even if it were possible to improve the amplitude-related spurs by running the LO through a digital circuit, then the mixer (especially digital mixers such as the Tayloe detector) would accomplish the same thing.JoeW3JDR----- Original Message -----From: FRANCIS CARCIASent: Saturday, December 31, 2005 4:17 PMSubject: Re: Fw: [softrock40] DDS spurs, was Got my 5.0....Now what do I need?Phase noise is related to the reference phase noise and spurs is a function of the dds.If the clock is multiplied in the dds the phase noise goes up also. The best way to go is use a high frequency oscillator without any multipliers. A high frequency saw oscillator would be perfect for a dds clock. A 600 mhz oscillator with 105 dBC phase noise at 1 kHz is common. A dds into dividers like flip flops or a comparator eliminates the effect or spurs over most ot the clock cycle. It only can change the time of the switch slightly. The rest of the cycle is not efected
Bill Tracey <kd5tfd@...> wrote:
I don't think one needs a spectrum analyzer to do the spur determination --
just wire up the SoftRock you intend to use it with and step thru the DDS
frequencies and see what the power spectrum is. Actually not too hard to
do with PowerSDR modified to control the DDS you're using. I sort of plan
to do it, although of late I'm spending more time with soldering iron in
hand than keyboard.
I don't believe Bob (N4HY) went with the sweep method - he looked at the #
of bits on the phase accumulator and the DAC on the DDS in question and
figured out where the low spur points should be on an algorithmic basis.
The higher the refclock the better I believe - at least in terms of phase
noise -- don't know how much of an impact it has on the spurs. I don't
know that the 3.3 v would make any difference -- don't think it would as I
think the primary cause of the spurs is round off error going into the
DAC. Don't know that a better LPF would help all that much as the
problematic spurs are the ones close in so they'd not be knocked down by
Since the SoftRock style receivers do not need a sin wave for the LO, it
would be nice to try using the comparator on the 9851 to generate a square
wave and see what that does to the spur situation. Even better would be to
take two 9851s and slave them together. I may try to do that with the DDS
60 board, although slaving them together for an IQ setup would probably be
better done with a board laid out for that purpose. And if one is going
to layout a board why not go with an IQ DDS such as the 9854 (yes it's a
bit of a soldering challenge!).
At 10:06 AM 12/31/2005, you wrote:
>Great info, Bill. It would be very useful to sweep the DSS-60, DDS-30 -
>QSD combination on a spectrum analyzer to see where the "hot points" are.
>I'm of the school where "real hardware doesn't lie". Maybe that's what
>N4HY did ? If they are rounding errors would you think they got
>better/worse with a higher ref clock input ? How about lower 3.3V voltage
>? Better DDS LPF (more poles) ? Add a divide by two D FF on the output ?
>I still think there is a pony in a divide by two Tayloe (not divide by
>four) and work on a reliable 50% duty cycle from the DDS clock output.
>That's what the COMBO cards have on them.
>73 Kees K5BCQ
- Double balanced mixers love square wave LO and produce less distortion due to the speed through the switch point. A square wave is easier to filter into a sine than going the other way.
KY1K <ky1k@...> wrote:
At 09:25 PM 1/22/2006, you wrote:
>Very true! I'm hoping some sharp fpga programmer figures out how to
>make a variable frequency square wave because we don't need no
>stinkin sine wave anyway.
I'm sure this is highly debatable. If your frequency is low enough
for a softrock-40 type application, then a square wave is fine.
But, most of us need sinewaves............
>The DDS has a way to go before it can compete with a good synthesizer design.
>It is easy it is quick but it is not clean enough to be called premium grade.
No argument here. DDS offers much though. A clean DDS would be a
giant leap forward in the softrock type receiver/transceiver
Does anyone know what frequency ECL logic can be clocked at?