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XOR divide by two clock driver

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  • n7ve
    Actgually, the first XOR gate is simply a squaring circuit. The negative feedback via the R/C simply biases the input to the on/off threshold of the gate.
    Message 1 of 13 , Dec 1, 2005
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      Actgually, the first XOR gate is simply a squaring circuit. The
      negative feedback via the R/C simply biases the input to the on/off
      threshold of the gate.

      This entire circuit only works if the input has a 50% duty cycle such
      as a good sinewave. If the input is not symetrical, the output will
      not be symetrical and the circuit will not work as intended.

      This is what they mean that this replaced the first flip flop. If you
      think of the clock circuit as two divide by two in series (not the
      best implementation for our phase shifted clocks), the purpose of the
      first divide by 2 is to square up the signal. If it is already
      symetrical, you could in theory skip the first divide by 2.

      The next two XORs are configured as an inverter and a non-inverter
      giving a non-inverted 2x clock and an inverted 2x clock. These two
      clocks feed a divide by two and the other a phase shifted version of
      that divide by two output.

      It is a nice circuit. I think it could be quite useful following a
      good sinewave source like a well designed crystal oscillator could
      produce. I am not sure that a DDS output is quite as symetrical, so
      it might not work quite as well unless the DDS output is properly low
      pass filtered for the frequency of interest.

      - Dan, N7VE
    • pvharman@arach.net.au
      Hi Phil, I used 48kbps and 16 bit samples to keep things simple for the first test. I also just used the left audio channel and the blocking version of the
      Message 2 of 13 , Dec 1, 2005
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        Hi Phil,

        I used 48kbps and 16 bit samples to keep things simple for the first test. I
        also just used the left audio channel and the blocking version of the
        PortAudio code - again a simple first test.

        I was looking at using one of the 2^n A/D states as a flag to indicate the
        next data word is say left. Having looked at the output of the Wolfson chip
        even with the input shorted you rarely see 0x0000 as data. With a bit of band
        noise we will be well above the zero threshold.

        So I am going to start with

        <0x0000><Left_data><Right_data><0x0000><Left_data><Right_data> etc

        Since data delivery using Bulk mode under USB2 is guaranteed I think that
        should be sufficient and the loss in dynamic range acceptable in practice.

        Bill suggested that we may not need to send the 0x0000 sync character as often
        as shown above given the reliability of the USB2 connection and I will try
        reducing its frequency once the above is working.

        I was also thinking of not bothering with testing under PortAudio but going
        straight to a PWM D/A converter in the FPGA for the Rx audio. That way I
        achieve my goal of removing the sound card and all the Windows drivers -
        reading and writing to the Wolfson and D/A's will take but a few lines of code
        then.

        Rather than a second A/D converter chip for the mic I was also going to look
        at using a PWM ramp feeding one input of a comparator and the mic signal the
        other. It may have no advantage over a single chip A/D, given the low cost of
        these nowadays, but a fun exercise anyway.

        I only wish that I had time years ago to lean to use FPGAs, they sure open a
        whole world of possibilities!

        73’s Phil… VK6APH



        Quoting Philip Covington <p.covington@...>:

        > Hi Phil,
        >
        > Good deal, sounds great! I am curious what sampling rate you were
        > running the Wolfson chip at and whether your were doing both channels
        > or just one for now? Also, what did you decide on for synchronization
        > of the audio frames between left and right channels?
        >
        > 73 de Phil N8VB
        >
        > On 12/1/05, pvharman@... <pvharman@...> wrote:
        > > Fellow Xyloeans,
        > >
        > > Last night I managed to get audio from the Wolfson A/D, via the FPGA and
        > FX2
        > >
        > > over the USB2 at 480Mbps to the PC and out over PortAudio to the speakers.
        > >
        > > For some reason PortAudio would hang after a few seconds but it was late
        > at
        > > night and not the time to start debugging.
        > >
        > > Having spent some time looking at VHDL I decided to start learning Verilog
        > > instead which proved to have a much shorter learning curve. I am just
        > > delighted with the Xylo board and how easy it is to program with the free
        > > Quartus II software.
        > >
        > > Next step is to fix the PortAudio bug and get it integrated into the
        > SDR1000
        > > software.
        > >
        > > 73's Phil...VK6APH
        > >
        > > _______________________________________________
        > > FlexRadio mailing list
        > > FlexRadio@...
        > > http://mail.flex-radio.biz/mailman/listinfo/flexradio_flex-radio.biz
        > >
        >
        >
        > --
        > Philip A Covington
        > http://www.philcovington.com
        >
      • Lyle Johnson
        ... Have you examined the material at this link? 73, Lyle KK7P
        Message 3 of 13 , Dec 1, 2005
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          > Rather than a second A/D converter chip for the mic I was also going to look
          > at using a PWM ramp feeding one input of a comparator and the mic signal the
          > other. It may have no advantage over a single chip A/D, given the low cost of
          > these nowadays, but a fun exercise anyway.

          Have you examined the material at this link?

          <http://www.microtelecom.it/digimit/techart.htm>

          73,

          Lyle KK7P
        • Lyle Johnson
          ... This is missed in most implementations. A low pass filter for the highest output frequency is constructed, so the signal becomes less pure as the
          Message 4 of 13 , Dec 1, 2005
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            > ...I am not sure that a DDS output is quite as symetrical, so
            > it might not work quite as well unless the DDS output is properly low
            > pass filtered for the frequency of interest.

            This is missed in most implementations. A low pass filter for the
            highest output frequency is constructed, so the signal becomes less pure
            as the frequency of the DDS is lowered. After all, a low pass filter at
            30 MHz won't suppress any components below that, so an LO for 80 meters
            has plenty of opportunity for spectral junk.

            I suspect 1/2 octave filters would work pretty well in a continuous
            coverage application, otherwise bandpass filters for the band of
            interest would probably work very well as long as the band if interest
            is not too wide.

            73,

            Lyle KK7P
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