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Re: Fw: Re: Fw: Re: [softrock40] Rocky and SR-40

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  • brainerd@bmi.net
    The output of the XOR gate is definitely NOT at 50%. You get a short pulse on the the rising and falling edges of the input clock. The output is only used to
    Message 1 of 13 , Dec 1, 2005
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      The output of the XOR gate is definitely NOT at 50%. You get a short pulse on the
      the rising and falling edges of the input clock. The output is only used to clock a 2 FF
      counter.

      Dave - WB6DHW

      On 1 Dec 2005 at 20:34, Bill Dumke wrote:

      > The only purpose of the XOR gate in question is to square up the clock
      > signal to a 50% duty cycle so you don't need to have another divide by 2
      > flip-flop do that for you. So the circuit works with a 2X clock instead
      > of a 4X clock. (E.g. the SoftRock 40 requires a 4X clock.)
      >
      > The XOR gate uses that RC network to sample some of the output and then
      > filter it with the capacitor. This DC voltage is then sent to the input
      > of the gate to adjust the biasing. Since it is a positive feedback
      > system, the bias adjusts itself until the output waveform has a 50 %
      > duty cycle square wave. (BTW the circuit will oscillate if the drive is
      > removed from the XOR gate.) (This can also be done with a couple of
      > NAND or NOR gates as well. All you need is a positive feedback line.)
      >
      > Bill WB5TCO
      >
      > KD5NWA wrote:
      >
      > > A doubler is created when you feed the signal into one pin of a XOR
      > > and a delayed version into the other pin, then what it really does is
      > > to detect edges on the input clock which for the right use doubles
      > > the frequency.
      > >
      > > That is not the case in this circuit, it tries to ensure that the
      > > input clock has a 50% duty cycle, then additional XOR gates provide a
      > > clock and inverted clock with equal delay so they stay synchronized.
      > > One clock clocks one FF and the opposite phase clocks the other, this
      > > makes to outputs of the FF's at 1X frequency but in Quadrature.
      > >
      > > The other day I mentioned using a 1X clock and feeding it into a MUX
      > > chip to generate 4 phases, the analog switch in this design, has a
      > > built in MUX. You don't enable each switch with a pin like in the
      > > SR-40 or the SR-5, you select one of four channels with two address
      > > pins to enable one at a time.
      > >
      > > Clever design, but not usable in the SR-40 without additional chips(
      > > a MUX chip) or a change in the Analog switch chip to one like the one
      > > used in this design which has a built in MUX, it would be usable in
      > > the SR-5 since it only uses two clocks not four like the SR-40 but
      > > you would need a 2X clock a disadvantage.
      > >
      > > At 07:46 PM 12/1/2005, you wrote:
      > > >Milt,
      > > >
      > > >Ahhh, didn't know about any RC network and yes you are right, that
      > > >would create a doubler ....but Dave said the XOR was in place of the
      > > >1st FF. If you use a XOR as a doubler with an RC network on one leg
      > > >you have anything BUT a 50% duty cycle waveform output and couldn't
      > > >eliminate the first FF. Maybe he uses a different FF and the XOR
      > > >output is for clocking only ? Have to look at that "....2001....."
      > > >circuit which was referenced.
      > > >
      > > >73 Kees K5BCQ
      > > >
      > > >w8nue@...>
      > > >To: <mailto:softrock40@yahoogroups.com>softrock40@yahoogroups.com
      > > >Date: Thu, 01 Dec 2005 18:47:00 -0600
      > > >Subject: Re: Fw: Re: [softrock40] Rocky and SR-40
      > > >Message-ID:
      > > <<mailto:438F9984.4050301@...>438F9984.4050301@...>
      > > >References:
      > > ><<mailto:20051201.171901.2264.12.windy10605@...>20051201.171901.2264.12.windy10605@...>
      > > >
      > > ><mailto:windy10605@...>windy10605@... wrote:
      > > >>OK !! it can be made to work OK. I notice the AD spec says 50% duty
      > > >>cycle +/-10% but I've never seen what it actually is across the
      > > >>frequency range. Some of the early info Alex published on Rocky
      > > >>shows a phase balance plot with around 12% and amplitude balance
      > > >>plot around 1.28. The typical comparator has both Q and
      > > >>Q(compliment) outputs so you probably don't need the XOR.
      > > >>
      > > >>73 Kees K5BCQ
      > > >Kees,
      > > >
      > > >I believe that the XOR is used as a frequency doubler. (If it has
      > > >an RC filter on one input--this causes an ouput pulse on both the
      > > >rising and falling edges of the input signal--i.e. at twice the
      > > >frequency of the input)
      > > >
      > > >Milt W8NUE
      > > >
      > > >
      > > >----------
      > > >YAHOO! GROUPS LINKS
      > > >
      > > > * Visit your group
      > > > "<http://groups.yahoo.com/group/softrock40>softrock40" on the web.
      > > > *
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      > > > *
      > > >
      > > <mailto:softrock40-unsubscribe@yahoogroups.com?subject=Unsubscribe>softrock40-unsubscribe@yahoogroups.com
      > >
      > > >
      > > > *
      > > > * Your use of Yahoo! Groups is subject to the
      > > > <http://docs.yahoo.com/info/terms/>Yahoo! Terms of Service.
      > > >
      > > >
      > > >----------
      > >
      > >
      > > Cecil Bayona
      > > KD5NWA
      > > www.qrpradio.com
      > >
      > > "I fail to see why doing the same thing over and over and getting the
      > > same results every time is insanity: I've almost proved it isn't;
      > > only a few more tests now and I'm sure results will differ this time
      > > ... "
      > >
      > >
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    • David Brainerd
      It appears I was confused on how that (the QRP2001) circuit works. After looking at it on my scope, it does produce an approx. 50% duty cycle. The R-C
      Message 2 of 13 , Dec 1, 2005
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        It appears I was confused on how that (the QRP2001) circuit works.
        After looking at it on my scope, it does produce an approx. 50% duty
        cycle. The R-C feedback in the first XOR biases the input at the
        midpoint. The sinewave input is then converted to a squarewave
        because of the very high gain of the XOR. I was confused between that
        circuit and the XOR doubler which uses both inputs.
        The circuit does, however, work quite well with the SDR and the
        Rocky software.

        Dave - WB6DHW

        --- In softrock40@yahoogroups.com, brainerd@b... wrote:
        >
        > The output of the XOR gate is definitely NOT at 50%. You get a
        short pulse on the
        > the rising and falling edges of the input clock. The output is only
        used to clock a 2 FF
        > counter.
        >
        > Dave - WB6DHW
        >
        > On 1 Dec 2005 at 20:34, Bill Dumke wrote:
        >
        > > The only purpose of the XOR gate in question is to square up the
        clock
        > > signal to a 50% duty cycle so you don't need to have another
        divide by 2
        > > flip-flop do that for you. So the circuit works with a 2X clock
        instead
        > > of a 4X clock. (E.g. the SoftRock 40 requires a 4X clock.)
        > >
        > > The XOR gate uses that RC network to sample some of the output and
        then
        > > filter it with the capacitor. This DC voltage is then sent to the
        input
        > > of the gate to adjust the biasing. Since it is a positive feedback
        > > system, the bias adjusts itself until the output waveform has a 50 %
        > > duty cycle square wave. (BTW the circuit will oscillate if the
        drive is
        > > removed from the XOR gate.) (This can also be done with a couple of
        > > NAND or NOR gates as well. All you need is a positive feedback line.)
        > >
        > > Bill WB5TCO
        > >
        > > KD5NWA wrote:
        > >
        > > > A doubler is created when you feed the signal into one pin of a XOR
        > > > and a delayed version into the other pin, then what it really
        does is
        > > > to detect edges on the input clock which for the right use doubles
        > > > the frequency.
        > > >
        > > > That is not the case in this circuit, it tries to ensure that the
        > > > input clock has a 50% duty cycle, then additional XOR gates
        provide a
        > > > clock and inverted clock with equal delay so they stay synchronized.
        > > > One clock clocks one FF and the opposite phase clocks the other,
        this
        > > > makes to outputs of the FF's at 1X frequency but in Quadrature.
        > > >
        > > > The other day I mentioned using a 1X clock and feeding it into a MUX
        > > > chip to generate 4 phases, the analog switch in this design, has a
        > > > built in MUX. You don't enable each switch with a pin like in the
        > > > SR-40 or the SR-5, you select one of four channels with two address
        > > > pins to enable one at a time.
        > > >
        > > > Clever design, but not usable in the SR-40 without additional chips(
        > > > a MUX chip) or a change in the Analog switch chip to one like
        the one
        > > > used in this design which has a built in MUX, it would be usable in
        > > > the SR-5 since it only uses two clocks not four like the SR-40 but
        > > > you would need a 2X clock a disadvantage.
        > > >
        > > > At 07:46 PM 12/1/2005, you wrote:
        > > > >Milt,
        > > > >
        > > > >Ahhh, didn't know about any RC network and yes you are right, that
        > > > >would create a doubler ....but Dave said the XOR was in place
        of the
        > > > >1st FF. If you use a XOR as a doubler with an RC network on one leg
        > > > >you have anything BUT a 50% duty cycle waveform output and couldn't
        > > > >eliminate the first FF. Maybe he uses a different FF and the XOR
        > > > >output is for clocking only ? Have to look at that "....2001....."
        > > > >circuit which was referenced.
        > > > >
        > > > >73 Kees K5BCQ
        > > > >
        > > > >w8nue@a...>
        > > > >To: <mailto:softrock40@yahoogroups.com>softrock40@yahoogroups.com
        > > > >Date: Thu, 01 Dec 2005 18:47:00 -0600
        > > > >Subject: Re: Fw: Re: [softrock40] Rocky and SR-40
        > > > >Message-ID:
        > > > <<mailto:438F9984.4050301@s...>438F9984.4050301@s...>
        > > > >References:
        > > >
        ><<mailto:20051201.171901.2264.12.windy10605@j...>20051201.171901.2264.12.windy10605@j...>
        > > > >
        > > > ><mailto:windy10605@j...>windy10605@j... wrote:
        > > > >>OK !! it can be made to work OK. I notice the AD spec says 50%
        duty
        > > > >>cycle +/-10% but I've never seen what it actually is across the
        > > > >>frequency range. Some of the early info Alex published on Rocky
        > > > >>shows a phase balance plot with around 12% and amplitude balance
        > > > >>plot around 1.28. The typical comparator has both Q and
        > > > >>Q(compliment) outputs so you probably don't need the XOR.
        > > > >>
        > > > >>73 Kees K5BCQ
        > > > >Kees,
        > > > >
        > > > >I believe that the XOR is used as a frequency doubler. (If it has
        > > > >an RC filter on one input--this causes an ouput pulse on both the
        > > > >rising and falling edges of the input signal--i.e. at twice the
        > > > >frequency of the input)
        > > > >
        > > > >Milt W8NUE
        > > > >
        > > > >
        > > > >----------
        > > > >YAHOO! GROUPS LINKS
        > > > >
        > > > > * Visit your group
        > > > > "<http://groups.yahoo.com/group/softrock40>softrock40" on the web.
        > > > > *
        > > > > * To unsubscribe from this group, send an email to:
        > > > > *
        > > > >
        > > >
        <mailto:softrock40-unsubscribe@yahoogroups.com?subject=Unsubscribe>softrock40-unsubscribe@yahoogroups.com

        > > >
        > > > >
        > > > > *
        > > > > * Your use of Yahoo! Groups is subject to the
        > > > > <http://docs.yahoo.com/info/terms/>Yahoo! Terms of Service.
        > > > >
        > > > >
        > > > >----------
        > > >
        > > >
        > > > Cecil Bayona
        > > > KD5NWA
        > > > www.qrpradio.com
        > > >
        > > > "I fail to see why doing the same thing over and over and
        getting the
        > > > same results every time is insanity: I've almost proved it isn't;
        > > > only a few more tests now and I'm sure results will differ this
        time
        > > > ... "
        > > >
        > > >
        > > >
        ------------------------------------------------------------------------
        > > > YAHOO! GROUPS LINKS
        > > >
        > > > * Visit your group "softrock40
        > > > <http://groups.yahoo.com/group/softrock40>" on the web.
        > > >
        > > > * To unsubscribe from this group, send an email to:
        > > > softrock40-unsubscribe@yahoogroups.com
        > > >
        <mailto:softrock40-unsubscribe@yahoogroups.com?subject=Unsubscribe>
        > > >
        > > > * Your use of Yahoo! Groups is subject to the Yahoo! Terms of
        > > > Service <http://docs.yahoo.com/info/terms/>.
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      • n7ve
        Actgually, the first XOR gate is simply a squaring circuit. The negative feedback via the R/C simply biases the input to the on/off threshold of the gate.
        Message 3 of 13 , Dec 1, 2005
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          Actgually, the first XOR gate is simply a squaring circuit. The
          negative feedback via the R/C simply biases the input to the on/off
          threshold of the gate.

          This entire circuit only works if the input has a 50% duty cycle such
          as a good sinewave. If the input is not symetrical, the output will
          not be symetrical and the circuit will not work as intended.

          This is what they mean that this replaced the first flip flop. If you
          think of the clock circuit as two divide by two in series (not the
          best implementation for our phase shifted clocks), the purpose of the
          first divide by 2 is to square up the signal. If it is already
          symetrical, you could in theory skip the first divide by 2.

          The next two XORs are configured as an inverter and a non-inverter
          giving a non-inverted 2x clock and an inverted 2x clock. These two
          clocks feed a divide by two and the other a phase shifted version of
          that divide by two output.

          It is a nice circuit. I think it could be quite useful following a
          good sinewave source like a well designed crystal oscillator could
          produce. I am not sure that a DDS output is quite as symetrical, so
          it might not work quite as well unless the DDS output is properly low
          pass filtered for the frequency of interest.

          - Dan, N7VE
        • pvharman@arach.net.au
          Hi Phil, I used 48kbps and 16 bit samples to keep things simple for the first test. I also just used the left audio channel and the blocking version of the
          Message 4 of 13 , Dec 1, 2005
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            Hi Phil,

            I used 48kbps and 16 bit samples to keep things simple for the first test. I
            also just used the left audio channel and the blocking version of the
            PortAudio code - again a simple first test.

            I was looking at using one of the 2^n A/D states as a flag to indicate the
            next data word is say left. Having looked at the output of the Wolfson chip
            even with the input shorted you rarely see 0x0000 as data. With a bit of band
            noise we will be well above the zero threshold.

            So I am going to start with

            <0x0000><Left_data><Right_data><0x0000><Left_data><Right_data> etc

            Since data delivery using Bulk mode under USB2 is guaranteed I think that
            should be sufficient and the loss in dynamic range acceptable in practice.

            Bill suggested that we may not need to send the 0x0000 sync character as often
            as shown above given the reliability of the USB2 connection and I will try
            reducing its frequency once the above is working.

            I was also thinking of not bothering with testing under PortAudio but going
            straight to a PWM D/A converter in the FPGA for the Rx audio. That way I
            achieve my goal of removing the sound card and all the Windows drivers -
            reading and writing to the Wolfson and D/A's will take but a few lines of code
            then.

            Rather than a second A/D converter chip for the mic I was also going to look
            at using a PWM ramp feeding one input of a comparator and the mic signal the
            other. It may have no advantage over a single chip A/D, given the low cost of
            these nowadays, but a fun exercise anyway.

            I only wish that I had time years ago to lean to use FPGAs, they sure open a
            whole world of possibilities!

            73’s Phil… VK6APH



            Quoting Philip Covington <p.covington@...>:

            > Hi Phil,
            >
            > Good deal, sounds great! I am curious what sampling rate you were
            > running the Wolfson chip at and whether your were doing both channels
            > or just one for now? Also, what did you decide on for synchronization
            > of the audio frames between left and right channels?
            >
            > 73 de Phil N8VB
            >
            > On 12/1/05, pvharman@... <pvharman@...> wrote:
            > > Fellow Xyloeans,
            > >
            > > Last night I managed to get audio from the Wolfson A/D, via the FPGA and
            > FX2
            > >
            > > over the USB2 at 480Mbps to the PC and out over PortAudio to the speakers.
            > >
            > > For some reason PortAudio would hang after a few seconds but it was late
            > at
            > > night and not the time to start debugging.
            > >
            > > Having spent some time looking at VHDL I decided to start learning Verilog
            > > instead which proved to have a much shorter learning curve. I am just
            > > delighted with the Xylo board and how easy it is to program with the free
            > > Quartus II software.
            > >
            > > Next step is to fix the PortAudio bug and get it integrated into the
            > SDR1000
            > > software.
            > >
            > > 73's Phil...VK6APH
            > >
            > > _______________________________________________
            > > FlexRadio mailing list
            > > FlexRadio@...
            > > http://mail.flex-radio.biz/mailman/listinfo/flexradio_flex-radio.biz
            > >
            >
            >
            > --
            > Philip A Covington
            > http://www.philcovington.com
            >
          • Lyle Johnson
            ... Have you examined the material at this link? 73, Lyle KK7P
            Message 5 of 13 , Dec 1, 2005
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              > Rather than a second A/D converter chip for the mic I was also going to look
              > at using a PWM ramp feeding one input of a comparator and the mic signal the
              > other. It may have no advantage over a single chip A/D, given the low cost of
              > these nowadays, but a fun exercise anyway.

              Have you examined the material at this link?

              <http://www.microtelecom.it/digimit/techart.htm>

              73,

              Lyle KK7P
            • Lyle Johnson
              ... This is missed in most implementations. A low pass filter for the highest output frequency is constructed, so the signal becomes less pure as the
              Message 6 of 13 , Dec 1, 2005
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                > ...I am not sure that a DDS output is quite as symetrical, so
                > it might not work quite as well unless the DDS output is properly low
                > pass filtered for the frequency of interest.

                This is missed in most implementations. A low pass filter for the
                highest output frequency is constructed, so the signal becomes less pure
                as the frequency of the DDS is lowered. After all, a low pass filter at
                30 MHz won't suppress any components below that, so an LO for 80 meters
                has plenty of opportunity for spectral junk.

                I suspect 1/2 octave filters would work pretty well in a continuous
                coverage application, otherwise bandpass filters for the band of
                interest would probably work very well as long as the band if interest
                is not too wide.

                73,

                Lyle KK7P
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