30703Re: [softrock40] DDS-34 / Re: Kits and a Website
- Feb 2, 2009At 05:26 PM 2/2/2009, you wrote:
>Well, seems to me that it is also a DDS, perhaps it is one with muchLook at the block diagram of a DDS and then look at the block diagram
>cleaner output, and maybe they could use it in the high end top
and you will see that they are not the same.
DDS ie; AD98XX a hybrid solution to generating a stable clock
* High frequency Reference clock, the output in order to be
reasonably clean can't approach the clock source due to Nyqist
issues, output typically limited to 1/3 reference clock.
* programmable divider whose output triggers a fractional addition
* fractional adder every clock from the divide adds the fraction
that controls the frequency to a large accumulator
* The upper bits of the accumulator are feed through a sine
lookup table into a D/A converter
* The D/A output is filtered and is used as the output
Very fine frequency control
Offset register could be added for phase control
Output of D/A subject to A/D common flaws such as uneven steps, or
feed through of bits causing errors in the output cause phase noise.
Noise from digital section can couple into the analog section for
increased phase noise.
Analog output must be turned back into a digital signal which we need
in the clock chain, this adds further to the noise.
Variable XO ie; XI570 a digital solution to generating a stable clock
* Built in crystal reference clock
* PLL multiplier with variable rate divide in the feedback to the
digital phase comparator, operates in the 2GHz 5 GHz range
* divider on the PLL out out
* Output is digital.
Output can be higher in frequency than the reference clock, as high as 1.7GHz
No Nyqist limits since we are dealing with digital circuits.
Entire chain is Digital for fewer noise issues.
No analog D/A with it's problems for cleaner output and way less phase noise
Output is digital, less phase noise since this what we wanted in the
first place to drive the I/Q clock generators
Changing the divider on the PLL cause a small delay before the
frequency stabilizes, no problem if all you are changing is the output divider.
They each have their unique weaknesses but overall I personally
prefer the SI570, there are cases though were it will fail for
example if you want to change the frequency repeatedly specially over
a range bigger than 3500ppm
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