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Re: ECM/FPGA Implementation Update

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  • Ron
    Actually I was just thinking more in terms of a simple ASCII text command line type interface. Ethernet interface IP designs are (I believe) freely
    Message 1 of 22 , Aug 1, 2005
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      Actually I was just thinking more in terms of a simple ASCII text
      command line type interface. Ethernet interface "IP" designs are (I
      believe) freely available, so the only work I would have to do is
      implement a simple ASCII command line interpreter that accepts an
      input (the number to be factored) and then spits a factor over the
      same port just as if it were talking over a TTY port. All it would
      take is a simple script of some sort (either Javascript or TCL would
      do) to connect an ethernet virtual socket to a virtual ethernet socket
      on the FPGA. Hopefully all the ethernet level protocol is part of the
      free ethernet interface design so that the FPGA would only have to
      worry about reading and writing data. That's the nice thing about
      FPGAs or hardware design in general - it can do everything truly in
      parallel without time slicing like computer operating systems do. Not
      sure what I'd do about collisions if more than one user were trying to
      access the device, but I could probably have it put out a busy message
      of some sort when it's busy calculating. It would be nice to at least
      implement Telnet, but I'm sure that would be too much of a burden for
      an FPGA.

      Regards,

      Ron
    • Ron
      Hi Folks, Consider this just a quick note to announce that tonight for the first time ever I HAVE SUCCESSFULLY TESTED MY VERILOG ECM DESIGN!!! It will be
      Message 2 of 22 , Sep 16 9:18 PM
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        Hi Folks,

        Consider this just a quick note to announce that tonight for the
        first time ever I HAVE SUCCESSFULLY TESTED MY VERILOG ECM DESIGN!!!

        It will be awhile before I have any hard statistics on how wide the
        data bus can be versus type of FPGA because there are an enormous
        number of choices of FPGAs, and quite a bit of "clean-up" work and
        testing remaining to be done, but initially at least the stats
        probably won't be very impressive. Most likely the maximum size
        composite it will be able to factor will be between 2^64 and 2^128 as
        a guess.

        Anyhow, for the first time in many years I feel like opening a bottle
        of some very old Cognac. :-)

        -- Ron
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