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Re: FPGA Implementation of Elliptic Curve method of integer factorization

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  • Hadley, Thomas H (Tom), ALABS
    FYI, for all of us who don t know the acronym FPGA, I looked it up and found: Short for Field-Programmable Gate Array, a type of logic chip that can be
    Message 1 of 11 , Jun 16, 2005
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      FYI, for all of us who don't know the acronym FPGA, I looked it up and found:

      "Short for Field-Programmable Gate Array, a type of logic chip that can be programmed. An FPGA is similar to a PLD (Programmable Logic Device?? - editor), but whereas PLDs are generally limited to hundreds of gates, FPGAs support thousands of gates. They are especially popular for prototyping integrated circuit designs. Once the design is set, hardwired chips are produced for faster performance."

      Tom Hadley

      -----Original Message-----
      From: primenumbers@yahoogroups.com
      [mailto:primenumbers@yahoogroups.com]On Behalf Of Ron
      Sent: Wednesday, June 15, 2005 7:26 PM
      To: primenumbers@yahoogroups.com
      Subject: [PrimeNumbers] Re: FPGA Implementation of Elliptic Curve method
      of integer factorization


      I'd like to express my appreciation to everyone on the forum who has
      helped answer the two mathematical conundrums I was faced with
      regarding implementation of the ECM in an FPGA:

      1. Question: Do I need a random number generator:
      Answer: NO, I can simply increment the curve parameters by one.

      2. Question: Does the starting point for the curve parameters matter:
      Answer: NO, it is independent of the number being factored.

      In fact I got more than I came here for - one good suggestion was
      that if I ever do need to implement a random number generator in
      hardware, shifting and XORing a polynomial is a much faster and
      easier method to implement in hardware than the multiply/add method I
      was considering.

      I'll post an update on the forum and probably send a couple of you an
      email whenever I get the elliptic curve generator module completed.
      That should probably be within a month or so as my health and
      inclination permit. At that point I'll be able to determine just how
      wide I can make the bus width and still have the design for the
      elliptic curve generation module fit into one of the Altera or
      Lattice 2 million gate FPGAs. :-)

      Best wishes and a big thank you to everyone,

      Ron





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