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2467Re: [powersdr-iq] Re: degrading Si570s?

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  • Bruce Tanner
    May 3, 2012
    • 0 Attachment
      Another 'keeper', Bob.  Thanks!



      On 5/3/2012 2:11 AM, g8voip wrote:
       

      Hi Eric,

      Adding some form of temperature compensation might improve the short term stability / variations a little, but never felt the need to do that here as the basic chip (CMOS) is good enough to run WSPR happily.

      I often run WSPR for 12 or more hours a day and apart from the initial warm up drift for the first 10 minutes or so, for the rest of the time I only see +/- a few Hz drift.

      All of my various SoftRock gear (13 different CMOS Si570's) exhibit the same sort of small variations, none are in fully enclosed cases, just open chassis on the bench, so subject to local temperature variations etc.

      I do check the calibration every couple of months against a GPS locked 10MHz standard but vary rarely bother to recalibrate them as the errors are very small.

      There is a newer high stability version of the CMOS Si570, forget the figures, but a lot more expensive plus needs some changes to the firmware driving it due to register changes. Fred PE0FKO's latest AVR firmware versions are able to 'sense' the device attached and use the correct format.

      73, Bob G8VOI

      --- In powersdr-iq@yahoogroups.com, "ericwd9" <ericwd9@...> wrote:
      >
      > Of seven Sis570's the average has been 9,000Hz deviation.
      > Has anyone seen or used the method of a thermistor
      > soldered to the case of the Sis570 as an oven?
      > Regards 73 Eric VK5ZAG
      >
      > --- In powersdr-iq@yahoogroups.com, "sv1eia" <sv1eia@> wrote:
      > >
      > > Well,
      > > Just to add a bit here.
      > > The thermal compensation does not mean that the variation number will be lower/small or even zero.
      > > Temperature stability is used to have a steady frequency during rig operation.
      > > Even with temperature control, you still might need to have a Si570 internal crystal calibration and a deviation number added.
      > >
      > > Internal crystal calibration and frequency stability are two separate things.
      > >
      > > Just my 2c.
      > >
      > > 73,
      > > Christos SV1EIA
      > >
      > >
      > > --- In powersdr-iq@yahoogroups.com, "Henk" <parasetguy@> wrote:
      > > >
      > > > Hello all,
      > > >
      > > > I built a LIMA-SDR. In this design by Bernd Wehner
      > > > DL9WB, are 2 fat R's placed on the Si570 to heat the chip up. An NTC is also put on it to control temperature. Interested in LIMA or want to download schematics? Go to http://www.darc.de/distrikte/l/02/sdr/handbuecher/ (German site)
      > > >
      > > > 73 de Henk - Parasetguy
      > > > http://www.paraset.nl/
      > > >
      > > >
      > > >
      > > > --- In powersdr-iq@yahoogroups.com, "The Silver Fox" <alan.r.hill@> wrote:
      > > > >
      > > > > The documentation implies that the chips are humidity sensitive and that
      > > > > should they misbehave, put them in an oven for a while.
      > > > >
      > > > > 73,
      > > > >
      > > > > Alan - W6ARH
      > > > >
      > > > >
      > > > >
      > > > > From: powersdr-iq@yahoogroups.com [mailto:powersdr-iq@yahoogroups.com] On
      > > > > Behalf Of sv1eia
      > > > > Sent: Tuesday, May 01, 2012 4:29 AM
      > > > > To: powersdr-iq@yahoogroups.com
      > > > > Subject: [powersdr-iq] Re: degrading Si570s?
      > > > >
      > > > >
      > > > >
      > > > >
      > > > >
      > > > > Hi Owen,
      > > > >
      > > > > Yes, I've seen numbers like these, having used more than 20 Si570 here.
      > > > > In the device datasheet
      > > > > -> http://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf
      > > > > page 13 on the table item
      > > > > "Internal Crystal Frequency Accuracy", it has 2000 ppm variation on
      > > > > 114.285.000 Hz so that goes if I'm not mistaken to about 228000 max
      > > > > variation, so since you're at about 60000 you're within limits.
      > > > >
      > > > > Most of the times, I've noticed higher variations with CMOS type whereas
      > > > > less variation with LVDS.
      > > > >
      > > > > 73,
      > > > > Christos SV1EIA
      > > > >
      > > > > --- In powersdr-iq@yahoogroups.com <mailto:powersdr-iq%40yahoogroups.com> ,
      > > > > "owen1936" <owen1936@> wrote:
      > > > > >
      > > > > > Over the past few years I've built three or four Si-570-based SDRs. To
      > > > > accurately calibrate them I've used a GPS-stabilized 10mHz reference input
      > > > > to a counter and the Expert/Clock Offset input in PSDR-IQ to correct
      > > > > frequency errors. Up until now I've never had to input any correction
      > > > > greater than -3900. But today in setting up for a possible new radio using
      > > > > PSDR-IQ v1.19.3.15 it required an offset of -60,530 to calibrate!
      > > > > >
      > > > > > I wonder if anybody else has seen this much required correction??
      > > > > >
      > > > > > 73,
      > > > > > Owen
      > > > > >
      > > > >
      > > >
      > >
      >



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