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2461RE: [powersdr-iq] Re: degrading Si570s?

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  • The Silver Fox
    May 1, 2012
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      The documentation implies that the chips are humidity sensitive and that should they misbehave, put them in an oven for a while.

      73,

      Alan – W6ARH

       

      From: powersdr-iq@yahoogroups.com [mailto:powersdr-iq@yahoogroups.com] On Behalf Of sv1eia
      Sent: Tuesday, May 01, 2012 4:29 AM
      To: powersdr-iq@yahoogroups.com
      Subject: [powersdr-iq] Re: degrading Si570s?

       

       

      Hi Owen,

      Yes, I've seen numbers like these, having used more than 20 Si570 here.
      In the device datasheet
      -> http://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf
      page 13 on the table item
      "Internal Crystal Frequency Accuracy", it has 2000 ppm variation on 114.285.000 Hz so that goes if I'm not mistaken to about 228000 max variation, so since you're at about 60000 you're within limits.

      Most of the times, I've noticed higher variations with CMOS type whereas less variation with LVDS.

      73,
      Christos SV1EIA

      --- In powersdr-iq@yahoogroups.com, "owen1936" <owen1936@...> wrote:
      >
      > Over the past few years I've built three or four Si-570-based SDRs. To accurately calibrate them I've used a GPS-stabilized 10mHz reference input to a counter and the Expert/Clock Offset input in PSDR-IQ to correct frequency errors. Up until now I've never had to input any correction greater than -3900. But today in setting up for a possible new radio using PSDR-IQ v1.19.3.15 it required an offset of -60,530 to calibrate!
      >
      > I wonder if anybody else has seen this much required correction??
      >
      > 73,
      > Owen
      >

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