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Re: [nslu2-linux] Re: nslu2 under the knife

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  • m. allan noah
    ... rxdata1 ball Y21 connected to right side of R128 rts1_n ball AC25 n/c cts1_n ball AB24 connected to left side of R142 txdata1 ball AA22 n/c so it looks
    Message 1 of 17 , Aug 18, 2004
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      On Wed, 18 Aug 2004, dyoung8888 wrote:

      > Thanks for the work!
      >
      > Is that to say then that the 2nd UART RX line goes somewhere? If
      > so, I'm in the middle of putting toegher my serial converter and
      > will attach a wire to the '3232 for that now (for a GPS for
      > instance).

      rxdata1 ball Y21 connected to right side of R128
      rts1_n ball AC25 n/c
      cts1_n ball AB24 connected to left side of R142
      txdata1 ball AA22 n/c

      so it looks like you can rx with it...

      allan

      >
      > D
      >
      > --- In nslu2-linux@yahoogroups.com, "m. allan noah" <anoah@p...>
      > wrote:
      > > i got a unit donated by Tommy B, and put the heat gun to it. after
      > a good
      > > cleaning, i got good news and bad news.
      > >
      > > the second ethernet and second uart tx lines are n/c, the other
      > lines are
      > > pulled. no way to get to the tx lines without removing the
      > processor. no
      > > good.
      > >
      > > but, the device side usb port is:
      > > USB_DNEG ball E21 connected to R130
      > > USB_DPOS ball F20 connected to R131
      > >
      > > and the jtag port is:
      > > TDI ball AE24 connected to R133
      > > TMS ball AF25 connected to R132
      > > TCK ball AF26 connected to R134/R138
      > > TDO ball AD23 connected to R137
      > > TRSTN ball AC22 connected to R135
      > >
      > > anyone else have something they want me to look for.
      > >
      > > allan
      > >
      > > --
      > > "so don't tell us it can't be done, putting down what you don't
      > know.
      > > money isn't our god, integrity will free our souls" - Max Cavalera
      >
      >
      >
      >
      >
      > Yahoo! Groups Links
      >
      >
      >
      >
      >
      >

      --
      "so don't tell us it can't be done, putting down what you don't know.
      money isn't our god, integrity will free our souls" - Max Cavalera
    • m. allan noah
      ... thank tommy, he bought it. i just took a torch to it :) it is sort of sickening, though, watching the solder and components drop off and know you dont have
      Message 2 of 17 , Aug 18, 2004
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        >
        > Really cool that you're doing this (and that you found JTAG
        > signals!).

        thank tommy, he bought it. i just took a torch to it :) it is sort of
        sickening, though, watching the solder and components drop off and know
        you dont have the ability to put it back. bit like sacking rome, i guess.

        >
        > I'm curious to find out why some people (including myself) are
        > seeing (significantly) slower xfer speeds when connected to a 'hub'
        > (half-duplex) vs a 'switch' (full duplex).
        >
        > As I said in an earlier message, a 'bug' in our design at work
        > (which also uses the IXP420) causes a lot of 'collision' errors when
        > in half-duplex mode. I wonder if the NSLU2 issue is similar?
        >

        ok, so i expect you to share what you found at work if i trace these. i am
        not going to be watson to your sherlock.

        spill it :)

        allan

        > So, a couple of signals I'd like to see are:
        >
        > ETH_CRS0 (pin AD4) (carrier sense port 0)
        > ETH_CRS1 (pin AF7) (carrier sense port 1)
        > ETH_RXDV0 (pin AD2) (RX data valid port 0)
        > ETH_RXDV1 (pin AE6) (RX data valid port 1)
        >
        > I don't know (off the top of my head) which ethernet port (0/1) is
        > used on the NSLU2. But, 'carrier sense' and 'RX data valid' for
        > that port should make it to the external PHY (RealTek, I believe).
        > Exactly where/how they connect to the PHY will help to determine
        > whether/not Linksys has the same 'bug' that we ran into @ work.
        >
        > Thanks,
        >
        > - Paulb
        >
        >
        >
        >
        >
        >
        >
        >
        > Yahoo! Groups Links
        >
        >
        >
        >
        >
        >

        --
        "so don't tell us it can't be done, putting down what you don't know.
        money isn't our god, integrity will free our souls" - Max Cavalera
      • paulbart1234
        ... when ... Well, of course I m trying to help solve the problem (assuming it s a similar problem), and use some of the lessons learned @ work to do it. In
        Message 3 of 17 , Aug 18, 2004
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          --- In nslu2-linux@yahoogroups.com, "m. allan noah" <anoah@p...>
          wrote:
          >> > As I said in an earlier message, a 'bug' in our design at work
          >> > (which also uses the IXP420) causes a lot of 'collision' errors
          when
          >> > in half-duplex mode. I wonder if the NSLU2 issue is similar?
          >> >
          >>
          >> ok, so i expect you to share what you found at work if i trace
          >> these. i am not going to be watson to your sherlock.
          >>
          >> spill it :)

          Well, of course I'm trying to help solve the problem (assuming it's
          a similar problem), and use some of the lessons learned @ work to do
          it.

          In our design, the external PHY chip didn't generate a
          separate 'carrier sense' signal. The people doing the hardware
          design mis-read the IXP420 docs that said you should tie the
          IXP's 'carrier sense' signal 'low' "if you aren't using this
          feature". They didn't realize that "feature" meant "half-duplex
          mode".

          So, we went merrily along thinking our product was working fine,
          until we started seeing packet loss all of a sudden. I narrowed it
          down to half-duplex mode (caused by using a hub), which lead me to
          find that the carrier sense input to the IXP420 was tied low.

          In our particular case, since our PHY didn't directly generate a
          separate carrier sense signal, it took a bit of configuration of the
          PHY to get it working (they had a mode where they mux their carrier
          sense state onto the 'rx data valid' signal, but the mode has to be
          set in software for it to work).

          I really don't expect the situation to be identical (totally
          different PHY chip), but knowing where the carrier sense signals go
          will help the investigation.

          - Paulb
        • rwhitby
          ... Allan, What do the seven test points on the board connect to? You can identify the test points on the front (component side) of the PCB by single solder
          Message 4 of 17 , Aug 18, 2004
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            > anyone else have something they want me to look for.

            Allan,

            What do the seven test points on the board connect to?

            You can identify the test points on the front (component side) of the
            PCB by single solder pads surrounded by a circular brown (not green)
            area.

            There is one near C21 (the big cap near the top of the unit), one
            near J4 (the Disk 2 port), one near the ready/status LED, one just
            above the ethernet port, one near the flash chip, one one the corner
            near the power socket, and one between the Y6 crystal and the buzzer.

            -- Rod
          • andrewpaprocki
            ... wrote: allan, does it look like the board does anything with the pci bus from the processor? (doesn t look like it). other ixp425 boards have ship with two
            Message 5 of 17 , Aug 18, 2004
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              --- In nslu2-linux@yahoogroups.com, "m. allan noah" <anoah@p...>
              wrote:

              allan,

              does it look like the board does anything with the pci bus from the
              processor? (doesn't look like it). other ixp425 boards have ship with
              two minipci slots hooked up to the processor. does it appear that the
              pci bus can be extended off this board onto a daughter card carrying
              1 or 2 minipci slots, or can we not get to those pins? just toying
              with the idea of internal 802.11a/b/g :)
            • m. allan noah
              i have not traced the pins, but i would assume that the pci bus connects to the NEC usb2.0 chip, and nothing else. allan ... -- so don t tell us it can t be
              Message 6 of 17 , Aug 19, 2004
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                i have not traced the pins, but i would assume that the pci bus connects
                to the NEC usb2.0 chip, and nothing else.

                allan

                On Thu, 19 Aug 2004, andrewpaprocki wrote:

                > --- In nslu2-linux@yahoogroups.com, "m. allan noah" <anoah@p...>
                > wrote:
                >
                > allan,
                >
                > does it look like the board does anything with the pci bus from the
                > processor? (doesn't look like it). other ixp425 boards have ship with
                > two minipci slots hooked up to the processor. does it appear that the
                > pci bus can be extended off this board onto a daughter card carrying
                > 1 or 2 minipci slots, or can we not get to those pins? just toying
                > with the idea of internal 802.11a/b/g :)
                >
                >
                >
                >
                >
                > Yahoo! Groups Links
                >
                >
                >
                >
                >
                >

                --
                "so don't tell us it can't be done, putting down what you don't know.
                money isn't our god, integrity will free our souls" - Max Cavalera
              • granz
                good work allan :) Q: Did you remove all components from the board (eg you now have a clean board)? If you did, how about taking some hirez photos of both
                Message 7 of 17 , Aug 19, 2004
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                  good work allan :)

                  Q: Did you remove all components from the board (eg you now have a
                  clean board)? If you did, how about taking some hirez photos of both
                  sides and posting them somewhere?

                  Thanks again for the effort to figure this out :)

                  -Dave G

                  --- In nslu2-linux@yahoogroups.com, "m. allan noah" <anoah@p...> wrote:
                  > i got a unit donated by Tommy B, and put the heat gun to it. after a
                  good
                  > cleaning, i got good news and bad news.
                  >
                  > the second ethernet and second uart tx lines are n/c, the other
                  lines are
                  > pulled. no way to get to the tx lines without removing the
                  processor. no
                  > good.
                  >
                  > but, the device side usb port is:
                  > USB_DNEG ball E21 connected to R130
                  > USB_DPOS ball F20 connected to R131
                  >
                  > and the jtag port is:
                  > TDI ball AE24 connected to R133
                  > TMS ball AF25 connected to R132
                  > TCK ball AF26 connected to R134/R138
                  > TDO ball AD23 connected to R137
                  > TRSTN ball AC22 connected to R135
                  >
                  > anyone else have something they want me to look for.
                  >
                  > allan
                  >
                  > --
                  > "so don't tell us it can't be done, putting down what you don't know.
                  > money isn't our god, integrity will free our souls" - Max Cavalera
                • m. allan noah
                  ... crs0 ball AD4 connected to phy #23 crs rxdv0 ball AD2 connected to phy #22 rxdv both traces pretty short, an inch or so, though the crs goes thru two vias
                  Message 8 of 17 , Aug 19, 2004
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                    On Thu, 19 Aug 2004, paulbart1234 wrote:
                    > I really don't expect the situation to be identical (totally
                    > different PHY chip), but knowing where the carrier sense signals go
                    > will help the investigation.

                    crs0 ball AD4 connected to phy #23 crs
                    rxdv0 ball AD2 connected to phy #22 rxdv

                    both traces pretty short, an inch or so, though the crs goes thru two vias
                    on the way.

                    crs1 af7 connected to bottom center pin of pr19
                    rxdv1 ae6 one of the top pins of pr19

                    does not look like what you saw?

                    allan

                    >
                    > - Paulb
                    >
                    >
                    >
                    >
                    >
                    >
                    > Yahoo! Groups Links
                    >
                    >
                    >
                    >
                    >
                    >
                    >
                    >

                    --
                    "so don't tell us it can't be done, putting down what you don't know.
                    money isn't our god, integrity will free our souls" - Max Cavalera
                  • m. allan noah
                    there are actually 10 of them on the component side, hidden under c21 and the power switch. they dont seem to connect to anything. i swept my meter over the
                    Message 9 of 17 , Aug 19, 2004
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                      there are actually 10 of them on the component side, hidden under c21 and
                      the power switch. they dont seem to connect to anything. i swept my meter
                      over the whole surface, and did not get any continuity. might just be
                      alignment marks for optical sensors during assembly?

                      allan

                      On Thu, 19 Aug 2004, rwhitby wrote:

                      > > anyone else have something they want me to look for.
                      >
                      > Allan,
                      >
                      > What do the seven test points on the board connect to?
                      >
                      > You can identify the test points on the front (component side) of the
                      > PCB by single solder pads surrounded by a circular brown (not green)
                      > area.
                      >
                      > There is one near C21 (the big cap near the top of the unit), one
                      > near J4 (the Disk 2 port), one near the ready/status LED, one just
                      > above the ethernet port, one near the flash chip, one one the corner
                      > near the power socket, and one between the Y6 crystal and the buzzer.
                      >
                      > -- Rod
                      >
                      >
                      >
                      >
                      >
                      > Yahoo! Groups Links
                      >
                      >
                      >
                      >
                      >
                      >

                      --
                      "so don't tell us it can't be done, putting down what you don't know.
                      money isn't our god, integrity will free our souls" - Max Cavalera
                    • paulbart1234
                      ... go ... two vias ... My immediate thought is: no, it doesn t look like it could be the same/similar problem. But, I ll take a look at the Realtek PHY
                      Message 10 of 17 , Aug 19, 2004
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                        --- In nslu2-linux@yahoogroups.com, "m. allan noah" <anoah@p...>
                        wrote:
                        > On Thu, 19 Aug 2004, paulbart1234 wrote:
                        > > I really don't expect the situation to be identical (totally
                        > > different PHY chip), but knowing where the carrier sense signals
                        go
                        > > will help the investigation.
                        >
                        > crs0 ball AD4 connected to phy #23 crs
                        > rxdv0 ball AD2 connected to phy #22 rxdv
                        >
                        > both traces pretty short, an inch or so, though the crs goes thru
                        two vias
                        > on the way.
                        >
                        > crs1 af7 connected to bottom center pin of pr19
                        > rxdv1 ae6 one of the top pins of pr19
                        >
                        > does not look like what you saw?

                        My immediate thought is: no, it doesn't look like it could be the
                        same/similar problem. But, I'll take a look at the Realtek PHY
                        datasheet and see if there's a chance that it's the same.

                        - Paulb
                      • paulbart1234
                        ... c21 and ... my meter ... be ... That was my thought. They don t look like the type of test points I m used to (I haven t seen the border around them
                        Message 11 of 17 , Aug 19, 2004
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                          --- In nslu2-linux@yahoogroups.com, "m. allan noah" <anoah@p...>
                          wrote:
                          > there are actually 10 of them on the component side, hidden under
                          c21 and
                          > the power switch. they dont seem to connect to anything. i swept
                          my meter
                          > over the whole surface, and did not get any continuity. might just
                          be
                          > alignment marks for optical sensors during assembly?

                          That was my thought. They don't look like the type of test points
                          I'm used to (I haven't seen the 'border' around them before) - so
                          thought it may have been for alignment.

                          The only thing is: why do they need 10 of them? 3 should be fine, I
                          think.

                          - Paulb
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