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Re: CMOS RAM HM6264LP-15 vs HM6264LP-10

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  • DougCrawford
    Brilliant! Sounds like a 1980 COMPUTE! April fools joke.
    Message 1 of 16 , Apr 18, 2013
      Brilliant! Sounds like a 1980 COMPUTE! April fools joke.

      >
      > If you can switch the chips fast enough, you can get a second bank of RAM without adding any hardware. :-)
      >
      >
      > - Dave
      >
    • David Riley
      ... It s usually for convenience, since a non-inverting buffer is usually two inverters in a row (one of which is tri-state). Inverting ones are faster and,
      Message 2 of 16 , Apr 18, 2013
        On Apr 18, 2013, at 9:28 AM, Systems Glitch wrote:

        > > Inverted BUS? I have not yet started trying to determine the purpose of the code.
        >
        > Some early bus structures were "inverted" in that a logic 0 was represented by what you would normally consider a logic 1 voltage. For TTL, this means that +3 and up is logic 0. The Ohio Scientific uses such a bus for their OSI-48 structure. Tranceivers usually exist with an inverted complement, like the 8T26/8T28.

        It's usually for convenience, since a non-inverting buffer is usually two inverters in a row (one of which is tri-state). Inverting ones are faster and, back when it mattered for individual ICs, were cheaper. For open-collector buses, they make lots of sense; for example, most DEC buses were inverted so that you could drive data directly to the drive transistor.

        In this case, if you had an inverted bus, it would make sense to store the ROM as inverted so you didn't have to put another buffer chip on the bus. If you're trying to disassemble it, just run it through a program to flip the bits.


        - Dave
      • DougCrawford
        Jonathan: That was a very keen observation. It ll be cool if you are right! I guess that would mean that data transferring to peripheral cards for the outside
        Message 3 of 16 , Apr 18, 2013
          Jonathan: That was a very keen observation.
          It'll be cool if you are right!
          I guess that would mean that data transferring to peripheral
          cards for the outside world would have to re-invert before
          shipping the data out... or that would be a mess!

          --- In midatlanticretro@yahoogroups.com, Systems Glitch <systems.glitch@...> wrote:
          >
          > > Inverted BUS? I have not yet started trying to determine the purpose of the code.
          >
          > Some early bus structures were "inverted" in that a logic 0 was represented by what you would normally consider a logic 1 voltage. For TTL, this means that +3 and up is logic 0. The Ohio Scientific uses such a bus for their OSI-48 structure. Tranceivers usually exist with an inverted complement, like the 8T26/8T28.
          >
          > Thanks,
          > Jonathan
          >
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