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Re: [midatlanticretro] CMOS RAM HM6264LP-15 vs HM6264LP-10

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  • B. Degnan
    ... nanosecond RAM, by definition, is fast enough for a 200 nanosecond application. I was trying to say that you can always substitute RAM, provided it s as
    Message 1 of 16 , Apr 17, 2013
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      >
      > --- On Wed, 4/17/13, Mr Ian Primus <ian_primus@...> wrote:
      >
      > > From: Mr Ian Primus <ian_primus@...>
      >
      > > In any application where, say,
      > > you need 200 nanosecond RAM, you can safely substitute 150
      > > or 100 - as long as it's fast enough.
      >
      > Just reread what I wrote here, and it's a little disjointed. 100 and 150
      nanosecond RAM, by definition, is fast enough for a 200 nanosecond
      application. I was trying to say that you can always substitute RAM,
      provided it's as fast or faster, than what you need.
      >

      Oh, I thought you meant if you switch the chips fast enough :-)
    • David Riley
      ... If you can switch the chips fast enough, you can get a second bank of RAM without adding any hardware. :-) - Dave
      Message 2 of 16 , Apr 17, 2013
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        On Apr 17, 2013, at 11:37 AM, "B. Degnan" <billdeg@...> wrote:

        > > > In any application where, say,
        > > > you need 200 nanosecond RAM, you can safely substitute 150
        > > > or 100 - as long as it's fast enough.
        > >
        > > Just reread what I wrote here, and it's a little disjointed. 100 and 150
        > nanosecond RAM, by definition, is fast enough for a 200 nanosecond
        > application. I was trying to say that you can always substitute RAM,
        > provided it's as fast or faster, than what you need.
        > >
        >
        > Oh, I thought you meant if you switch the chips fast enough :-)

        If you can switch the chips fast enough, you can get a second bank of RAM without adding any hardware. :-)


        - Dave
      • Dave McGuire
        ... Well, you can, actually. It s pretty easy to calculate the required memory access time based on processor datasheet parameters and the clock rate. In
        Message 3 of 16 , Apr 17, 2013
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          On 04/17/2013 11:35 AM, B. Degnan wrote:
          >> 15 nanoseconds is *slower* than 10 nanosecond. Also, the -10 means 100
          > nanosecond in this case. Likewise, -15 means 150 nanosecond. So, your 150
          > nanosecond RAM is slower than the original RAM.
          >>
          >> The substitution might work - it just depends on how fast the RAM really
          > needs to be. In any application where, say, you need 200 nanosecond RAM,
          > you can safely substitute 150 or 100 - as long as it's fast enough.
          >>
          >> But, it's safe to try - it won't hurt anything if it doesn't work.
          >>
          >> What computer is this for?
          >>
          >
          > understood, no real way to know unless you try.

          Well, you can, actually. It's pretty easy to calculate the required
          memory access time based on processor datasheet parameters and the clock
          rate. In some cases (like in the case of wait states) the design of the
          memory system is also relevant in the calculation.

          > I did assume 15 was slower
          > too, from the data sheet anyway. Not sure if this was a gold band/
          > silverband resistor analogy and did not really matter in the vintage world
          > compared with newer stuff.

          It does, though. However, RAM chips (and many others) are "binned"
          during production. All of those chips were designed to run at (say)
          100ns. They were all tested, and ones that made the 100ns+margin spec
          were binned as 100ns. Ones that didn't, but did pass for 120ns, were
          binned for THAT speed...etc. Then they're packaged and labeled accordingly.

          In many cases that margin will save you, if you need to get it working
          and you don't have a chip that's fast enough on hand. As Ian said, it's
          safe to try.

          -Dave

          --
          Dave McGuire, AK4HZ
          New Kensington, PA
        • joshbensadon
          Hi Bill, Saw your post on COSMAC ELF. I don t have an account on Vintagecomputers, it s too late at night right now to make one. I looked at the ROM dumps,
          Message 4 of 16 , Apr 17, 2013
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            Hi Bill,

            Saw your post on COSMAC ELF. I don't have an account on Vintagecomputers, it's too late at night right now to make one.

            I looked at the ROM dumps, and at first I thought it looked nothing like the 1802 machine code. Then I inverted all the bits in my head and it started making sense.

            Could this system be using an inverted bus?

            :)J
          • B Degnan
            ... Btw ...You don t need an account to send a note via the contact form. Inverted BUS? I have not yet started trying to determine the purpose of the code. --
            Message 5 of 16 , Apr 18, 2013
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              joshbensadon <no_reply@yahoogroups.com> wrote:

              >Hi Bill,
              >
              >Saw your post on COSMAC ELF. I don't have an account on
              >Vintagecomputers, it's too late at night right now to make one.
              >
              >I looked at the ROM dumps, and at first I thought it looked nothing
              >like the 1802 machine code. Then I inverted all the bits in my head
              >and it started making sense.
              >
              >Could this system be using an inverted bus?
              >
              >:)J
              >
              >
              >
              >
              >------------------------------------
              >
              >Yahoo! Groups Links
              >
              >
              >
              Btw ...You don't need an account to send a note via the contact form.

              Inverted BUS? I have not yet started trying to determine the purpose of the code.

              --
              Sent from my PDP 8/e.
            • Systems Glitch
              ... Some early bus structures were inverted in that a logic 0 was represented by what you would normally consider a logic 1 voltage. For TTL, this means that
              Message 6 of 16 , Apr 18, 2013
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                > Inverted BUS? I have not yet started trying to determine the purpose of the code.

                Some early bus structures were "inverted" in that a logic 0 was represented by what you would normally consider a logic 1 voltage. For TTL, this means that +3 and up is logic 0. The Ohio Scientific uses such a bus for their OSI-48 structure. Tranceivers usually exist with an inverted complement, like the 8T26/8T28.

                Thanks,
                Jonathan
              • joshbensadon
                ... The FD1771 FDC chip also uses an inverted data bus. The benefits of an inverted bus is the use of an inverted tranceiver which are typically twice as fast
                Message 7 of 16 , Apr 18, 2013
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                  --- In midatlanticretro@yahoogroups.com, Systems Glitch <systems.glitch@...> wrote:
                  >
                  > > Inverted BUS? I have not yet started trying to determine the purpose of the code.
                  >
                  > Some early bus structures were "inverted" in that a logic 0 was represented by what you would normally consider a logic 1 voltage. For TTL, this means that +3 and up is logic 0. The Ohio Scientific uses such a bus for their OSI-48 structure. Tranceivers usually exist with an inverted complement, like the 8T26/8T28.
                  >
                  > Thanks,
                  > Jonathan


                  The FD1771 FDC chip also uses an inverted data bus. The benefits of an inverted bus is the use of an inverted tranceiver which are typically twice as fast as the non-inverted types. This is especially true for those vintage chips. Another benefit is the simplified tranceiver (only 1 set of transistors) which makes sense for these very early experimental CPU's.

                  :)J
                • DougCrawford
                  Brilliant! Sounds like a 1980 COMPUTE! April fools joke.
                  Message 8 of 16 , Apr 18, 2013
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                    Brilliant! Sounds like a 1980 COMPUTE! April fools joke.

                    >
                    > If you can switch the chips fast enough, you can get a second bank of RAM without adding any hardware. :-)
                    >
                    >
                    > - Dave
                    >
                  • David Riley
                    ... It s usually for convenience, since a non-inverting buffer is usually two inverters in a row (one of which is tri-state). Inverting ones are faster and,
                    Message 9 of 16 , Apr 18, 2013
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                      On Apr 18, 2013, at 9:28 AM, Systems Glitch wrote:

                      > > Inverted BUS? I have not yet started trying to determine the purpose of the code.
                      >
                      > Some early bus structures were "inverted" in that a logic 0 was represented by what you would normally consider a logic 1 voltage. For TTL, this means that +3 and up is logic 0. The Ohio Scientific uses such a bus for their OSI-48 structure. Tranceivers usually exist with an inverted complement, like the 8T26/8T28.

                      It's usually for convenience, since a non-inverting buffer is usually two inverters in a row (one of which is tri-state). Inverting ones are faster and, back when it mattered for individual ICs, were cheaper. For open-collector buses, they make lots of sense; for example, most DEC buses were inverted so that you could drive data directly to the drive transistor.

                      In this case, if you had an inverted bus, it would make sense to store the ROM as inverted so you didn't have to put another buffer chip on the bus. If you're trying to disassemble it, just run it through a program to flip the bits.


                      - Dave
                    • DougCrawford
                      Jonathan: That was a very keen observation. It ll be cool if you are right! I guess that would mean that data transferring to peripheral cards for the outside
                      Message 10 of 16 , Apr 18, 2013
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                        Jonathan: That was a very keen observation.
                        It'll be cool if you are right!
                        I guess that would mean that data transferring to peripheral
                        cards for the outside world would have to re-invert before
                        shipping the data out... or that would be a mess!

                        --- In midatlanticretro@yahoogroups.com, Systems Glitch <systems.glitch@...> wrote:
                        >
                        > > Inverted BUS? I have not yet started trying to determine the purpose of the code.
                        >
                        > Some early bus structures were "inverted" in that a logic 0 was represented by what you would normally consider a logic 1 voltage. For TTL, this means that +3 and up is logic 0. The Ohio Scientific uses such a bus for their OSI-48 structure. Tranceivers usually exist with an inverted complement, like the 8T26/8T28.
                        >
                        > Thanks,
                        > Jonathan
                        >
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