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29130Re: IMSAI 8080

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  • joshbensadon
    Jan 31, 2013
      --- In midatlanticretro@yahoogroups.com, Systems Glitch wrote:
      > Some of the older hardware was designed to take advantage of some very specific aspects of the 8080's timing. I discovered this with my Solid State Music PB-1, which uses extremely long wait states to burn EPROMs mapped in as RAM. It sort-of worked some of the time with my Cromemco ZPU (only at 2 MHz), and refused to burn more than a byte or two with my IMS Z80 board at any speed.
      > It's an usual use of wait states, but I couldn't make full use of my PB-1 until I picked up a true 8080 based CPU board.
      > Thanks,
      > Jonathan

      Yeah, the Tarbell 1101 Floppy Disk Controller is another board that depends on the STATUS byte being present during pSYNC pulses (an 8080A feature). To be specific, it's the BOOT ROM (if used).

      During BOOT, it disables CPU MREAD & MWRITE and recreates them but keeps MREAD local to the BOOT ROM while MWRITE can access the RAM on the S-100 BUS. This way, it can execute the BOOT ROM at address 0000 to 001F, while still storing data in RAM at those same addresses.

      I really enjoy the creative solutions that were used back then.

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