Loading ...
Sorry, an error occurred while loading the content.

Re: Q - Primo EM-23 (Nakamichi) capsules - SNR

Expand Messages
  • userno232000
    OK, I have some better measurements and the noise of my circuit is the same as the electrical noise when substituting a 51pf capacitor for the capsule ie. the
    Message 1 of 31 , Apr 1 2:03 PM
    • 0 Attachment
      OK, I have some better measurements and the noise of my circuit is
      the same as the electrical noise when substituting a 51pf capacitor
      for the capsule ie. the stock FET and the resistor limit the noise to
      about 16-17dBA. So time to order some 5G resistors and scour the junk
      box for some better FET's.

      BTW Roger, I know it feels bad but reverse engineering is actually
      protected by law. If you buy someone's circuit and trace the
      schematic you can do whatever you want with it. Post it, sell it, and
      if it's not patented put it in your own product. There is no such
      thing as a circuit copyright, the disclaimers notwithstanding if you
      post a circuit that is not protected by patent anyone can use it as
      they wish (in the US at least).

      --- In micbuilders@yahoogroups.com, "krokavadet" <roger.barbara@...>
      wrote:
      >
      > The Telinga circuit was in the files section here. I have removed
      > it, because I did not want to upset Telinga... I believe Scott
      > Wurcer and Eric Benjamin gave some comments, the Miller effect was
      > mentioned. Please, take a look in the files section,
      primomicamp.pdf.
      >
      > Roger Gustavsson
      >
      >
    • userno232000
      Basicly the noise limit on a FET is that of a resistance of roughly 2/3 (1/gm). This is a little worse than a bipolar (1/2 of 1/(gm)). But FET s have no base
      Message 31 of 31 , Apr 15 8:10 AM
      • 0 Attachment
        Basicly the noise limit on a FET is that of a resistance of roughly
        2/3 (1/gm). This is a little worse than a bipolar (1/2 of 1/(gm)).
        But FET's have no base current noise, so you keep paralleling them to
        get the noise down. Eventually though the input capacitance
        attenuates the input signal and you stop improving SNR. This is why a
        50pF Ciss FET is a bad match on a 5pF minature capsule. This is
        simplistic, of course, paralleling a hundred 10mA Idss FET's has
        other problems. I was tempted once, to measure the noise of a single
        pc board contact, but it wasn't worth the time or effort.

        The (1/gm)*Cin is actually a better way to look at it for charge amps
        because the noise is related to the square root of the channel
        resistance. You might find that some FET's just act like smaller ones
        in parallel. This figure of merit weeds out processes that are more
        optimum for the job.

        --- In micbuilders@yahoogroups.com, Richard Lee <ricardo@...> wrote:
        >
        > Dear Mr Wurcer,
        >
        > > But what is the exact form of the figure of merit you quote?
        > >
        > > Are you saying there is no way to do a 1nV/rtHz FET without
        Ciss~50p?
        >
        > Is the FoM
        >
        > 1 / (Vn * Ciss) ? Vn : nV/rtHz Ciss : pF
        >
        > I'm really asking if the relation is linear inverse or more
        complicated.
        >
        > >The gm has to be in the 1/50 Ohm or so region to give you your 1nV
        of noise.
        >
        > Thanks for this. Have you got a analytical or even a rule of thumb
        for
        >
        > gm vs noise potential?
        >
        >
        >
        >
        > --
        > No virus found in this outgoing message.
        > Checked by AVG Free Edition.
        > Version: 7.5.446 / Virus Database: 269.4.0/760 - Release Date:
        13/04/07 20:04
        >
      Your message has been successfully submitted and would be delivered to recipients shortly.