Section 6.2 applies also to the SDRAM. When the EDAC is enabled, a store byte (or half-word) will generate a read cycle first, then insert the stored byte, andjiri_gaisler
We get an tt = 0x2B, data store error on our GR712RC when using SDRAM with EDAC enabled and we would like to understand better what causes this kind of trap asthalionath
Zohaib: thanks for your reply! Can I have a way to solve the problem or only try to avoid write "0" to that bit?mahf108
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