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Re: [leon_sparc] synthesis and routing of 2-core leon smp on digilent virtex 2p

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  • Jiri Gaisler
    You design does not fit the fpga. Either configure it to be smaller (reduce some functionality) or use synplify for synthesis (which produces smaller netlists
    Message 1 of 3 , Feb 13, 2007
      You design does not fit the fpga. Either configure it to
      be smaller (reduce some functionality) or use synplify
      for synthesis (which produces smaller netlists than XST).

      Jiri.

      Abhishek Bhattacharjee wrote:
      > I managed to comment out the relevant portions in the.xcf file and the bitstream is being generated now. However, the utilization summary I am getting is puzzling me:
      >
      > Slices: 14247 utilized out of a possible 13696 (104%)
      > A warning is generated at the bottom regarding this...
      >
      > How is the above possible? I have not actually tried to implement the bitstream on the FPGA but is there a design error? I just have 2 cores in this design -- is the logic utilization too high for the Virtex 2P to support?
      >
      > -Abhishek
      >
      > Abhishek Bhattacharjee <abttje@...> wrote: Hi everyone -
      >
      > I am trying to synthesize and route a 2 core smp on a Digilent Virtex2Pro board but am experiencing some difficulties (I am using Xilinx ISE 8.2 with service pack 3). Firstly, I went to the appropriate designs folder (leon3-digilent-xup) and ran "make xconfig" and carried out the necessary configuration. The only changes I made were to set the number of processors to 2. I also do not have any off-chip DRAM and have to use the BRAM as the shared memory and so I added AHB on chip memory through xconfig. When I run the ise flow (make ise), I receive errors regarding the presence of the DRAM netlist settings from the ucf file. However, after commenting these out, I am still getting the following problem:
      >
      > Building and optimizing final netlist ...
      > Annotating constraints using XCF file 'leon3mp.xcf'
      > WARNING:Xst:1665 - Line 5: Can not define group with TNM_NET on INST or PIN. Constraint ignored.
      > Last warning will be issued only once.
      > ERROR:Xst:1370 - Line 9: Signal name clkml not found in design.
      > ERROR:Xst:1370 - Line 12: Signal name ddrlock not found in design.
      > ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
      > ERROR:Xst:1341 - XCF parsing failed
      >
      > I am a bit confused about what the .xcf file is...what is its exact function? Is it to be used with the ucf file? And in general, what is the procedure for commenting out the appropriate material from the .ucf and .xcf files?
      > Thanks!
      >
      > -Abhishek
      >
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