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UART interrupt problem

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  • Kamudu Kamesh
    Hello all, We are working on ATSAM3S4C Cortex-M3 controller. We have written a sample code which enables UART0 receive interrupt. The interrupt is not being
    Message 1 of 3 , May 24 11:45 PM
      Hello all,
      We are working on ATSAM3S4C Cortex-M3 controller. We have written a sample code which enables UART0 receive interrupt. The interrupt is not being generated when a character is received by the controller. However when we read the serial receive register (polling) we are able to retrieve the character. Serial receive interrupt is being enabled, the interrupt handler is in place etc. One more strange thing we noticed is the address in the vector table and that of the service routine(s). There is a 1 byte difference. For example:

      Table entry:
      400004:    004003f1     .word    0x004003f1    // reset exception entry

      Actual location of code
      004003f0 <ResetException>:

      Why is there a difference of 1 in the address and how is the controller able to execute the code properly?

      Thanks in advance for the help.

      Regards
      Kam.
    • Jean-Marc Koller
      ... Bit 0 means that the instruction set to be used is the THUMB mode, which has to be set, according to the ARM documentation (DDI0337E, cortex M3 R1 P1, page
      Message 2 of 3 , May 25 9:52 AM
        On 25 mai 2013, at 08:45, Kamudu Kamesh <kkamudu@...> wrote:

        > being enabled, the interrupt handler is in place etc. One more strange thing we noticed is the address in the vector table and that of the service routine(s). There is a 1 byte difference. For example:
        >
        > Table entry:
        > 400004: 004003f1 .word 0x004003f1 // reset exception entry
        >
        > Actual location of code
        > 004003f0 <ResetException>:
        >
        > Why is there a difference of 1 in the address and how is the controller able to execute the code properly?

        Bit 0 means that the instruction set to be used is the THUMB mode, which has to be set, according to the ARM documentation (DDI0337E, cortex M3 R1 P1, page 96, chapter 5.1), even if the core doesn't know anything about the ARM instruction set:
        "
        Vector table entries are ARM/Thumb interworking compatible.

        This causes bit [0] of the vector value to load into the EPSR T-bit on exception entry. Creating a table entry with bit [0] clear generates an INVSTATE fault on the first instruction of the handler corresponding to this vector.
        "

        So, it's fully normal to have an odd address in the vector table!
      • Kamudu Kamesh
        ... Thank you very much Jean-Marc Koller. That explains everything. I was all along thinking that the address stored in the table is pure 32 bit address which
        Message 3 of 3 , May 25 8:20 PM

          >Bit 0 means that the instruction set to be used is the THUMB mode, which has to be set, according to the ARM documentation (DDI0337E, cortex M3 R1 >P1, page 96, chapter 5.1), even if the core doesn't know anything about the ARM instruction set:
          >"
          >Vector table entries are ARM/Thumb interworking compatible.
          >
          >This causes bit [0] of the vector value to load into the EPSR T-bit on exception entry. Creating a table entry with bit [0] clear generates an INVSTATE fault >on the first instruction of the handler corresponding to this vector.
          >"
          >
          >So, it's fully normal to have an odd address in the vector table!

          Thank you very much Jean-Marc Koller. That explains everything. I was all along thinking that the address stored in the table is pure 32 bit address which gets copied into to the PC.

          Regards
          Kamesh



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