Loading ...
Sorry, an error occurred while loading the content.

5199Re: [gnuarm] UART interrupt problem

Expand Messages
  • Kamudu Kamesh
    May 25, 2013

      >Bit 0 means that the instruction set to be used is the THUMB mode, which has to be set, according to the ARM documentation (DDI0337E, cortex M3 R1 >P1, page 96, chapter 5.1), even if the core doesn't know anything about the ARM instruction set:
      >Vector table entries are ARM/Thumb interworking compatible.
      >This causes bit [0] of the vector value to load into the EPSR T-bit on exception entry. Creating a table entry with bit [0] clear generates an INVSTATE fault >on the first instruction of the handler corresponding to this vector.
      >So, it's fully normal to have an odd address in the vector table!

      Thank you very much Jean-Marc Koller. That explains everything. I was all along thinking that the address stored in the table is pure 32 bit address which gets copied into to the PC.


    • Show all 3 messages in this topic