On 25 mai 2013, at 08:45, Kamudu Kamesh <kkamudu@...
> being enabled, the interrupt handler is in place etc. One more strange thing we noticed is the address in the vector table and that of the service routine(s). There is a 1 byte difference. For example:
> Table entry:
> 400004: 004003f1 .word 0x004003f1 // reset exception entry
> Actual location of code
> 004003f0 <ResetException>:
> Why is there a difference of 1 in the address and how is the controller able to execute the code properly?
Bit 0 means that the instruction set to be used is the THUMB mode, which has to be set, according to the ARM documentation (DDI0337E, cortex M3 R1 P1, page 96, chapter 5.1), even if the core doesn't know anything about the ARM instruction set:
Vector table entries are ARM/Thumb interworking compatible.
This causes bit  of the vector value to load into the EPSR T-bit on exception entry. Creating a table entry with bit  clear generates an INVSTATE fault on the first instruction of the handler corresponding to this vector.
So, it's fully normal to have an odd address in the vector table!