Re: [fpga-cpu] New minimal CPU design
> > Jan Gray somehow managed to fit a 4 operator ALU into aThank you!
> > single LUT per bit. (In the GR0040) Is there any documentation on
> > this ? So maybe there is a way to reduce the ALU size to 6 CLBs.
> Some of it is here: http://www.fpgacpu.org/log/nov00.html#001112.
> Some of it is hinted at in the GR0000 paper here:
> in section 3.12.
> Now then. Say you build a 4-bit ALU using this techniques. 4 LUTs.Thats a pretty interesting idea. But how do we load data from the ram ?
> And say you attach that to a 16 entry x 4-bit LUT RAM (another 4 LUTs,
> or 8 if you make it dual-port RAM). And say you add a 2-bit counter (2
> LUTs) to sequence through LSB addresses 00, 01, 10, and 11 to that LUT
> RAM. Now you have a simple datapath with 4 16-bit registers,
> nybble-serial, that should easily run at 100 MHz (25 MHz for each 16-bit
> operation). Total cost of datapath: 10-14 LUTs (3-4 Virtex CLBs; 2
> Virtex2 CLBs).
I fear another MUX is required, at least to load constants.
> To hook that up to a 512x8 or 256x16 BRAM for program and data storage,Hm. that could substitute for the adress register, if we dont allow
> you need another 8 or 9 FFs for a PC and/or address register. These FFs
> can share the same handful of CLBs with the aforementioned LUTs. The
> instruction register can be the BRAM output register.
indexed adressing modes. This would simplify the control a bit.
OTOH the PC could be mapped to the registerfile, but this would
double the amount of cycles per instruction. (well, 8 cycles for a dual
registerfile, 12 cycles for single ported)
The adress register could have an incrementer. This would make flexible
instruction encoding easy. (register to register ops: 1 byte, immediate ops
- Sunday Ed Corter (hey that me) wrote
I am almost done with an Auto rotate and shift module
(Verilog). Module is programmable for mode of
operation ( sh \ rot ) and a count of operations is
set. When the operand is written . the module does the
N Op's and flags Done.
The module description and usage is available at
there's a zip file for download that contains all of
the files ( 3 for the module ) and all of the models
sim files including the bench.
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