Re: [fpga-cpu] New minimal CPU design
> > But well, actually I was rather referring to the designNo chance to get anything else into the CPLD, there is not even
> > being minimal in respect to resource usage. 31 CPLD macrocells
> > are maybe comparable to ~16 Spartan CLBs, which is even less than
> > 20% of a Spartan XCS05. (But you cant compare CPLDs and FPGAs
> > anyways.. the design is optimized for CPLD usage and would
> > be suboptimal for a FPGA).
> That is hard to say what a good small model is . A shift right
> and jump zero would be nice instructions if you had the room.
enough room left for a synch. reset. :)
And btw. are there really that many uses for a zero flag ? I see
it being useful for bit comparisons, but in most arithmetic routines
it is sufficient to have a greater-than or less-than compare.
The equal-to compare can easily be done by an add #255, jcc ..
Wide NOR gates can eat quite a bit of resources.
> > I'd be interested to know about minimal FPGA cpu designs.Hm.. that would imply a 9bit PC. The datapath would probably
> > Since the ALU can be minimized easily due to carry chains,
> > the main problem is probably to optimize the control.
> Historically 12 bits have been the minimum real cpu design.
> I suspect a clean design
> - ADD ac = ac + n , toggle carry
> - NOR ac = ac nor n
> - SHR ac = rcr ac , shift carry
> - DCA ac = 0 ; n = ac
> - JC if(cy) pc = n
> -JZ if(z) pc = n
> -JMP pc = n
> -JSR ac = pc ,pc = n
> would be about three times the size of a small 8 bit processor.
take 12+1+9+2=24 CLbs (ALU, Carry, PC/Adreg, Z-Flag ) thats not
too much. The control probably would not increase that much over
an 8 Bit CPU, so it is maybe just twice as big.
Jan Gray somehow managed to fit a 4 operator ALU into a single
LUT per bit. (In the GR0040) Is there any documentation on
this ? So maybe there is a way to reduce the ALU size to 6 CLBs.
The DCA instruction is neat, however when I looked at the example
for my CPU, which uses STA, I noticed that none of them could
benefit from a DCA instruction.
- Sunday Ed Corter (hey that me) wrote
I am almost done with an Auto rotate and shift module
(Verilog). Module is programmable for mode of
operation ( sh \ rot ) and a count of operations is
set. When the operand is written . the module does the
N Op's and flags Done.
The module description and usage is available at
there's a zip file for download that contains all of
the files ( 3 for the module ) and all of the models
sim files including the bench.
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