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RE: [fpga-cpu] Timings

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  • Jan Gray
    ... I can t speak for Virtex-II, with its active (buffered) interconnect fabric, which gets most nets down to
    Message 1 of 7 , Oct 19, 2001
      > Do you think it's possible to get this working >50MHz after
      > floorplanning, or is it not worth the effort ?

      I can't speak for Virtex-II, with its active (buffered) interconnect
      fabric, which gets most nets down to <2 ns delays, but for XC4000X and
      Virtex/E, floorplanning can certainly halve critical path net delays,
      and, as importantly, make the delays predictable so you have terra firma
      upon which to make methodical implementation decisions.

      Hand-in-hand with floorplanning is a certain amount of careful
      technology mapping: structuring your design so critical paths map into a
      small number of 4-LUT logic levels.

      Jan Gray, Gray Research LLC
    • Ed Corter
      ... I have alot of experience with the VirtexE Please email me the info on what synhtesis tool and what version of mapper / Place and rount is being used and
      Message 2 of 7 , Oct 19, 2001
        --- Jan Gray <jsgray@...> wrote:
        > > Do you think it's possible to get this working
        > >50MHz after
        > > floorplanning, or is it not worth the effort ?
        >
        > I can't speak for Virtex-II, with its active
        > (buffered) interconnect
        > fabric, which gets most nets down to <2 ns delays,
        > but for XC4000X and
        > Virtex/E, floorplanning can certainly halve critical
        > path net delays,
        > and, as importantly, make the delays predictable so
        > you have terra firma
        > upon which to make methodical implementation
        > decisions.
        >
        > Hand-in-hand with floorplanning is a certain amount
        > of careful
        > technology mapping: structuring your design so
        > critical paths map into a
        > small number of 4-LUT logic levels.
        >
        > Jan Gray, Gray Research LLC
        >
        >
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        >

        I have alot of experience with the VirtexE

        Please email me the info on what synhtesis tool and
        what version of mapper / Place and rount is being used
        and any timing constraints bneing used

        artiedc@...

        we have sucsussfully done an OFDM modem desing that
        spanned 4 1000E's and ran at 93.333 mHz using
        SynplifyPro for synthesis and constraint generation.

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      • robfinch@sympatico.ca
        ... First, I made a boo-boo. I was looking at the wrong timing report. Tools report my design will work at 56MHz not 95MHz (I kind of wondered the design being
        Message 3 of 7 , Oct 19, 2001
          --- In fpga-cpu@y..., Ed Corter <artiedc@y...> wrote:
          >
          >
          > Please email me the info on what synhtesis tool and
          > what version of mapper / Place and rount is being used
          > and any timing constraints bneing used
          >
          > artiedc@y...
          >
          First, I made a boo-boo. I was looking at the wrong timing report.
          Tools report my design will work at 56MHz not 95MHz (I kind of
          wondered the design being in a -5 SpartanII). That kind of explains
          most of the difference, although it still quite a step down to 25MHz
          after PAR.

          I'm using the tools provided with Webpack 4.1 (XST). Are there any
          other good free tools out there ?

          I'd like to make my design available somehow (".edn" format ?) when I
          finish. If I floorplan the design is it possible retain the
          floorplanning in the .edn file ?
        • Ed Corter
          ... I m using the tools provided with Webpack 4.1 (XST). Are there any other good free tools out there ? Thats the same that I use at home; however, I batch
          Message 4 of 7 , Oct 19, 2001
            --- robfinch@... wrote:
            > --- In fpga-cpu@y..., Ed Corter <artiedc@y...>
            > wrote:

            I'm using the tools provided with Webpack 4.1 (XST).
            Are there any
            other good free tools out there ?

            Thats the same that I use at home; however, I batch
            execute all steps of the build.. except the verilog
            compile is still done with ise GUI.

            I'd like to make my design available somehow (".edn"
            format ?) when I
            finish. If I floorplan the design is it possible
            retain the
            floorplanning in the .edn file ?

            Answer is yes..
            In the IDE there is an option for creatin a Macro. The
            macro retains the loc's and routing.
            When a macro is being instantiated into another
            design it must not have the IO buffers: just net
            ports. Also the Macro serach path must be provided at
            build time.




            =====


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