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Re: [XP] XP vs. Hardware Development

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  • Kenneth Tyler
    ... checked, then it goes out for fabrication. ... Thanks so much for the further details. How is the layout done and checked ? That seems to be an
    Message 1 of 8 , Dec 2, 2001
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      > 1) it generally takes about a week to get the board layout done and
      checked, then it goes out for fabrication.
      >
      Thanks so much for the further details. How is the layout "done and checked"
      ? That seems to be an interesting point. Also, is it possible to simulate
      these boards with software (even if the result was much slower than the
      actual board ) ?

      Kenneth Tyler
    • Russel Hill
      ... AFAIK: The board layout is done by HW engineers using CAD tools. The layout is constrained by physical connectors, device pinouts, standard form factors
      Message 2 of 8 , Dec 2, 2001
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        At 08:12 AM 12/2/01 -0800, Kenneth Tyler wrote:
        >Thanks so much for the further details. How is the layout "done and checked"
        >? That seems to be an interesting point. Also, is it possible to simulate
        >these boards with software (even if the result was much slower than the
        >actual board ) ?

        AFAIK: The board layout is done by HW engineers using CAD tools. The layout is constrained by physical connectors, device pinouts, standard form factors (eg. PCI, cPCI, VME, ...) and such. The connectors and devices are placed, more-or-less by hand. Then a layout tool grinds through the schematic routing traces from pin to pin.

        Unfortunately, the automagic trace routing isn't 100% trusted. In fact, we've had to send boards out a second time because the router dropped a few traces. So, we currently check the layout packages against the schematic by hand.

        Re: Simulations - Yes it's possible to simulate the boards. Unfortunately, the simulation software isn't anything like an xUnit. The HW designer usually crafts simulation 'scripts' to stimulate selected portions of the hardware, then examines the resulting output by hand. The output generally looks like a logic analyzer output, with as many as several dozen individual wave forms displayed.

        Hardware simulations are also subject to discrepancies between a device's specification and the device's actual behavior. An example of this was a chunk of RAM we used to capture data. According to the spec, we were using it correctly and the simulations looked good (I actually have to 'trust' the HW designer on this... not something I like to do). In actual operation, the devices didn't behave as expected. We ended up with corrupted data. To get around this, we had to make a few cuts and add a few jumpers, which were later incorporated into the board.

        Also, when the boards involve an FPGA (most of ours do), we often produce a raw board design long before the behavior inside the FPGA is implemented. The board is designed with an adequate supply of memory, FPGA resources, connectors, and necessary 'glue logic'. Then the internal behavior of the FPGA is implemented. Yes, we've had instances where we've had to cut out functionality because the FPGA wasn't big enough. We've also had instances where new requirements required more RAM that was on the board. This is analogous to specifying a computer with sufficient horsepower for the application (you hope) before the app is complete. Sometimes you have to get a faster, bigger, badder box to make run the app. You gotta start somewhere...

        The behavior implemented inside the FPGA is where I think XP style development could really help. I can't tell you how many times a HW type implemented a feature that we didn't need or want. Then the HW designer say's we'll "thank him in 6 months".. (hasn't happened) When this goes well, we ignore the extra features. When this goes badly, we either work around the extra features, or (in rare cases) get the HW type to fix or remove them. It's generally been a lot easier to ignore or work around the bonus features that to either get the HW type to fix or remove them.
      • Dinwiddie, George
        Back when clock rates were not so high, we d incrementally develop boards using wire-wrap before committing to a PC card. Even now, it seems that you can
        Message 3 of 8 , Dec 3, 2001
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          Back when clock rates were not so high, we'd incrementally
          develop boards using wire-wrap before committing to a PC card.
          Even now, it seems that you can produce lab PC cards pretty
          quickly and evolve the design using an xacto knife and jumpers.

          - George [who's even built 3-dimensional circuits with no
          board for a short-term hardware "spike."]

          > -----Original Message-----
          > From: Russel Hill
          >
          > I am currently working on a project where hardware
          > development plays a large role. I am interested in hearing
          > from anyone who has experience with XP in a combined HW/SW
          > development..
          >
          > The portion of the HW development that involves PC board
          > layout has constraints that pose challenges agile processes.
          > At a few thousand dollars and a few weeks per iteration of a
          > PC board, there are compelling reasons for a larger portion
          > of DUF than we are used too. However, once the board layout
          > is proven, it seems like ASIC or FPGA design could enjoy a
          > development cycle similar to software development (but not
          > quite identical). I'm not even certain that a FPGA
          > configuration isn't software since it's a binary file which
          > is loaded at run-time.
          >
          > Does anyone have experience with XP (or other agile
          > processes) used for (or in conjunction with) hardware development?
        • Russel Hill
          ... More than once I ve seen a chip, glued to the board, pins in the air. Jumper wires connect this device to the rest of the board. Not surprisingly, we
          Message 4 of 8 , Dec 3, 2001
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            At 01:37 PM 12/3/01 -0500, Dinwiddie, George wrote:
            >Back when clock rates were not so high, we'd incrementally
            >develop boards using wire-wrap before committing to a PC card.
            >Even now, it seems that you can produce lab PC cards pretty
            >quickly and evolve the design using an xacto knife and jumpers.

            More than once I've seen a chip, glued to the board, pins in the air. Jumper wires connect this device to the rest of the board. Not surprisingly, we call this 'putting on a dead bug.'

            Today there are significant challenges to the Xacto and jumper approach.

            1) Multilayer boards - The trace you need to cut may be buried inside the board. You can drill through it, but sometimes you can't get to it wthoug cutting other traces.

            2) Surface mount devices w/ Ultra-fine pins (and pin pitch) - Requires the use of a stereo microscope to work on them.

            3) BGA - The entire bottom surface of a device is covered with little nubbs for electrical connectivity, Makes it hard to 'lift a pin'. Checking the solder joints requires a xray.

            The tools and skills required to doctor these boards are difficult to find, expensive and boards doctored like this are fragile, not suited for industrial environments. In fact we do use these techniques to get prototypes running. Then we have to re-layout the board prior to shipping. We don't ship boards with jumpers.

            I happen to have one prototype board on my desk... it's been there for about a year. Nobody wants it because it's so covered with jumpers. Perfect for me. I get to keep my integration hardware.



            > - George [who's even built 3-dimensional circuits with no
            > board for a short-term hardware "spike."]

            Reminds me of an analog designer I used to work with. He'd chicken-wire his circuits like this, dead bugging the devices on a copper clad sheet, which he'd use as a ground plane.
          • Dinwiddie, George
            ... Yes, I understand that can be a problem. I never had to deal with more than 4 layers (buried power and ground), so I didn t have that problem. Perhaps
            Message 5 of 8 , Dec 4, 2001
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              Russel Hill replied:
              >
              > 1) Multilayer boards - The trace you need to cut may be
              > buried inside the board. You can drill through it, but
              > sometimes you can't get to it wthoug cutting other traces.

              Yes, I understand that can be a problem. I never had to deal
              with more than 4 layers (buried power and ground), so I didn't
              have that problem. Perhaps you can work with the board layout
              people to make sure that certain signals run on the surface
              at some point during their travel. Hardware testability can
              affect the design.

              > 2) Surface mount devices w/ Ultra-fine pins (and pin pitch) -
              > Requires the use of a stereo microscope to work on them.

              I once had to use a jumper on a custom LSI chip. There was
              a connector that didn't; it was on the wrong layer of silicon.
              I set up two non-amplified probes to get the signal across a
              seven micron gap. It was a PITA. Everytime I fried a chip,
              it took a half-hour or more to get the new chip ready to test.

              > Reminds me of an analog designer I used to work with. He'd
              > chicken-wire his circuits like this, dead bugging the devices
              > on a copper clad sheet, which he'd use as a ground plane.

              That's a great technique for analog. I've known lots of people
              to do that.

              - George
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