PNAS 2013 110 (37) E3468-E3476; published ahead of print July 22, 2013, doi:10.1073/pnas.1212083110
Synthesizing cognition in neuromorphic electronic systems
Emre Neftci, Jonathan Binas, Ueli Rutishauser, Elisabetta Chicca, Giacomo Indiveri, and Rodney J. Douglas
Neuromorphic emulations express the dynamics of neural systems in analogous electronic circuits, offering a distributed, low-power technology for constructing intelligent systems. However, neuromorphic circuits are inherently imprecise and noisy, and there has been no systematic method for configuring reliable behavioral dynamics on these substrates. We describe such a method, which is able to install simple cognitive behavior on the neuromorphic substrate. Our approach casts light on the general question of how the neuronal circuits of the brain, and also future neuromorphic technologies, could implement cognitive behavior in a principled manner.
The quest to implement intelligent processing in electronic neuromorphic systems lacks methods for achieving reliable behavioral dynamics on substrates of inherently imprecise and noisy neurons. Here we report a solution to this problem that involves first mapping an unreliable hardware layer of spiking silicon neurons into an abstract computational layer composed of generic reliable subnetworks of model neurons and then composing the target behavioral dynamics as a “soft state machine” running on these reliable subnets. In the first step, the neural networks of the abstract layer are realized on the hardware substrate by mapping the neuron circuit bias voltages to the model parameters. This mapping is obtained by an automatic method in which the electronic circuit biases are calibrated against the model parameters by a series of population activity measurements. The abstract computational layer is formed by configuring neural networks as generic soft winner-take-all subnetworks that provide reliable processing by virtue of their active gain, signal restoration, and multistability. The necessary states and transitions of the desired high-level behavior are then easily embedded in the computational layer by introducing only sparse connections between some neurons of the various subnets. We demonstrate this synthesis method for a neuromorphic sensory agent that performs real-time context-dependent classification of motion patterns observed by a silicon retina.
"Our key insight in dealing with such systems is that the uncertain hardware elements should by simple local mappings contribute to a more computationally stable intermediate layer. In our example, it is this intermediate abstract neural architecture that couples the behavioral model to the hardware (or even biological) neuronal implementation. This intermediate layer serves three purposes. First, it provides computational primitives on which behaviors are easily cast and learned. Second, these primitives provide basic signal processing properties necessary for steering and stabilizing processing such as signal gain, signal restoration (17), and multistability (45). Finally, the layer of primitives hides the details and variability of the neuronal hardware implementation from the behavioral level. Biology may have discovered a similar strategy, for example in the neocortex, which appears to be a sheet of essentially similar local circuitry that can be configured to satisfy a variety of processing tasks (12)."
"Overall, the important insight of this paper is that the abstract layer composed of sWTA provides reliable processing on the unreliable underlying neuromorphic hardware, while simplifying the programming of high-level behavior. This approach is analogous to the manner in which software is used to program and compile computational processes in general purpose digital computers, except that the underlying neuromorphic hardware is radically different from digital ones in both system concept and electronic implementation. The approach is sufficiently general to be used on a wide range of electronic neural networks that have reconfigurable synaptic weights and reprogrammable connectivity (6, 7, 61)."
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