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Checkpoint on the Shield Adapter and SPI Software

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  • bill rowe
    I m going to stabilize the Shield Adapter hardware and related SPI software for now. The Schematic version 6 uses an 8 pin AVR to generate a 1 Mhz clock that
    Message 1 of 2 , Dec 20, 2013
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      I'm going to stabilize the Shield Adapter hardware and related SPI software for now.  The Schematic version 6 uses an 8 pin AVR to generate a 1 Mhz clock that is triggered automatically when the 1802 writes to the 4021 Master Out Shift Register(MOSR) with OUT 6.  The AVR generates 8 pulses on SCK and the inverse /SCK.  SCK notifies the slave to read the output of MOSR on MOSI and it latches the signal from the slave on MISO into the 74595 Master Input Shift Register(MISR).  /SCK is used to advance the bits in MOSR and to clock the shifted bits in MISR from the shift register of the 74595 to the storage register where it can be read by the 1802 with INP 6.
       
       

      At 1 mhz you need to leave one instruction time between accesses to the SPI registers.  I know how to fix this but it's not a big problem so I'm leaving it for now.  The 1802 code shown includes 4 SPI routines:

      • spixfer loads 1 byte out to MOSR and reads one from MISR.  This is the standard SPI sequence
      • spiSend loads 1 byte to MOSR but does not bother with the readback
      • spiSendN transfers N bytes to MOSR as quickly as it can
      • spiReceiveN sends garbage out to MOSR and reads MISR into a supplied buffer

      There doesn't seem to be a need for an individual spiReceive or an spixferN.


       
       

      I'm going to leave the hardware and software alone for now. If I do another run I would do the following in priority sequence:

      1. Gate the signal that loads MOSR with TPB and /MRD.  Even with a 1mhz clock there would be no delay needed between accesses
      2. Use the cpu clock and a counter to replace the AVR
      3. replace the 4021 with a 74165 to allow the clock speed to go above 2.5 mhz.
    • bill_rowe@rogers.com
      I tried including the images inline as well as attaching them but it just left big blank gaps in the message. Oh well, live and learn. ... -spixfer loads 1
      Message 2 of 2 , Dec 20, 2013
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        I tried including the images inline as well as attaching them but it just left big blank gaps in the message. Oh well, live and learn.

        --- In cosmacelf@yahoogroups.com, bill rowe <bill_rowe_ottawa@...> wrote:
        >
        > I'm going to stabilize the Shield Adapter hardware and related SPI software for now. The Schematic version 6 uses an 8 pin AVR to generate a 1 Mhz clock that is triggered automatically when the 1802 writes to the 4021 Master Out Shift Register(MOSR) with OUT 6. The AVR generates 8 pulses on SCK and the inverse /SCK. SCK notifies the slave to read the output of MOSR on MOSI and it latches the signal from the slave on MISO into the 74595 Master Input Shift Register(MISR). /SCK is used to advance the bits in MOSR and to clock the shifted bits in MISR from the shift register of the 74595 to the storage register where it can be read by the 1802 with INP 6.

        > At 1 mhz you need to leave one instruction time between accesses to the SPI registers. I know how to fix this but it's not a big problem so I'm leaving it for now. The 1802 code shown includes 4 SPI routines:
        -spixfer loads 1 byte out to MOSR and reads one from MISR. This is the standard SPI sequence
        -spiSend loads 1 byte to MOSR but does not bother with the readback
        -spiSendN transfers N bytes to MOSR as quickly as it can
        -spiReceiveN sends garbage out to MOSR and reads MISR into a supplied buffer
        There doesn't seem to be a need for an individual spiReceive or an spixferN.

        > I'm going to leave the hardware and software alone for now. If I do another run I would do the following in priority sequence:
        -Gate the signal that loads MOSR with TPB and /MRD. Even with a 1mhz clock there would be no delay needed between accesses
        -Use the cpu clock and a counter to replace the AVR
        -Replace the 4021 with a 74165 to allow the clock speed to go above 2.5 mhz.
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