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Re: [cosmacelf] I thought this would be easy but... - logic signal combination

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  • Lee Hart
    ... I suppose there a dozen ways to do it. A lot depends on what your definition of a good solution is. My thought pattern is something like this: AVR is the
    Message 1 of 13 , Jun 22, 2013
    • 0 Attachment
      On 6/22/2013 1:33 PM, bill rowe wrote:
      >
      >
      > I have a parallel-in-serial-out shift register(CD4021) that triggers on
      > a positive edge. it's currently used by the avr microprocessor on the
      > olduino board to read the data bus. Once the register is loaded, the avr
      > can read bit 8 right away, then it toggles the clock signal, reads bit
      > 7, etc. I want the 1802 to also be able to trigger the shift register on
      > the trailing edge of N1 - it needs to be the trailing edge so a
      > peripheral can read it on the leading edge. I've drawn the two cases below
      >
      > The N line pulses are maybe 3 microseconds long, the avr's probably
      > shorter but they could be whatever I want.
      >
      > I guess I don't really care what happens at the xx point so the output
      > could stay high but not forever because sooner or later the avr would
      > want to clock it.
      >
      > Could I use a one-shot? a flip-flop? I'm stabbing in the dark here. I
      > could have the AVR assert a separate control line when it wants to clock
      > but adding another signal doesn't seem like a good idea. The AVR could
      > invert it's signal though, or anything else that seemed to help.
      >
      > Oh, I don't care if the avr's pulse gets delayed as long as I know about
      > it so that's like an OR of the two signals with a multi-us delay.
      >
      > Any help gratefully accepted. I have been chewing on this a while!

      I suppose there a dozen ways to do it. A lot depends on what your
      definition of a "good" solution is. My thought pattern is something like
      this:

      AVR is the same as OUT, so all you need between them is an OR gate.
      ______
      N circuit___\ \
      AVR___| OR O----OUT
      /_____/

      OR gates are less common than NOR gates. But gates come in packages of
      4, so we have 3 extra gates for "free". We can use one section as an
      inverter. Now we have:
      ______ ______
      N circuit___\ NOR \ __\ NOR \
      AVR___| A O---|__| B O----OUT
      /_____/ /_____/

      N from the 1802 is delayed; so you need a one-shot (or equivalent). It
      needs to trigger on the falling edge of N, generate a positive pulse,
      and turn itself back off without any other signals.

      We still have 2 sections of that NOR gate. We can use an RC delay
      network to make a delayed version of N. Then combine them with a gate,
      so that OUT is only high when N is low AND delayed N is still high.

      1802 N signal__--------________
      RC delayed N ______--------____
      OUT signal __________----____

      You already need an OR gate, and they come in packages of 4. Note that
      OUT is high when N is low; so we also need an inverter. So use this circuit:
      ______
      N_____________________________\ NOR \
      | _____ __| D O----N circuit
      |__/\/\_______\ NOR\ | /_____/
      R1 |____| C O---
      _|_ /____/
      C1 ___
      |
      gnd

      Now add the AVR OR gate to this circuit.
      ______
      N___________________________\ NOR \ ______ ______
      | _____ __| D O--------\ NOR \ __\ NOR \
      |_/\/\______\ NOR\ | /_____/ AVR___| A O--|__| B O---OUT
      R1 |___| C O--- /_____/ /_____/
      _|_ /____/
      C1 ___
      |
      gnd

      The whole thing is done with one quad NOR gate, 1 resistor, and 1 capacitor.

      --
      A good scientist is a person with original ideas. A good engineer is
      a person who makes a design that works with as few original ideas as
      possible. There are no prima donnas in engineering. -- Freeman Dyson

      --
      Lee A. Hart, http://www.sunrise-ev.com/LeesEVs.htm
    • bill rowe
      Thanks lee. Sadly I have never been able to read an ascii art message on the board or from outlook. What I get using courier shows below. I m guessing
      Message 2 of 13 , Jun 23, 2013
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        Thanks lee.  Sadly I have never been able to read an ascii art message on the board or from outlook. What I get using courier shows below.   I'm guessing something is stripping blanks or tabs from the beginning of lines?
         

         
         

         


        To: cosmacelf@yahoogroups.com
        From: leeahart@...
        Date: Sat, 22 Jun 2013 17:38:53 -0500
        Subject: Re: [cosmacelf] I thought this would be easy but... - logic signal combination

         
        On 6/22/2013 1:33 PM, bill rowe wrote:
        >
        >
        > I have a parallel-in-serial-out shift register(CD4021) that triggers on
        > a positive edge. it's currently used by the avr microprocessor on the
        > olduino board to read the data bus. Once the register is loaded, the avr
        > can read bit 8 right away, then it toggles the clock signal, reads bit
        > 7, etc. I want the 1802 to also be able to trigger the shift register on
        > the trailing edge of N1 - it needs to be the trailing edge so a
        > peripheral can read it on the leading edge. I've drawn the two cases below
        >
        > The N line pulses are maybe 3 microseconds long, the avr's probably
        > shorter but they could be whatever I want.
        >
        > I guess I don't really care what happens at the xx point so the output
        > could stay high but not forever because sooner or later the avr would
        > want to clock it.
        >
        > Could I use a one-shot? a flip-flop? I'm stabbing in the dark here. I
        > could have the AVR assert a separate control line when it wants to clock
        > but adding another signal doesn't seem like a good idea. The AVR could
        > invert it's signal though, or anything else that seemed to help.
        >
        > Oh, I don't care if the avr's pulse gets delayed as long as I know about
        > it so that's like an OR of the two signals with a multi-us delay.
        >
        > Any help gratefully accepted. I have been chewing on this a while!

        I suppose there a dozen ways to do it. A lot depends on what your
        definition of a "good" solution is. My thought pattern is something like
        this:

        AVR is the same as OUT, so all you need between them is an OR gate.
        ______
        N circuit___\ \
        AVR___| OR O----OUT
        /_____/

        OR gates are less common than NOR gates. But gates come in packages of
        4, so we have 3 extra gates for "free". We can use one section as an
        inverter. Now we have:
        ______ ______
        N circuit___\ NOR \ __\ NOR \
        AVR___| A O---|__| B O----OUT
        /_____/ /_____/

        N from the 1802 is delayed; so you need a one-shot (or equivalent). It
        needs to trigger on the falling edge of N, generate a positive pulse,
        and turn itself back off without any other signals.

        We still have 2 sections of that NOR gate. We can use an RC delay
        network to make a delayed version of N. Then combine them with a gate,
        so that OUT is only high when N is low AND delayed N is still high.

        1802 N signal__--------________
        RC delayed N ______--------____
        OUT signal __________----____

        You already need an OR gate, and they come in packages of 4. Note that
        OUT is high when N is low; so we also need an inverter. So use this circuit:
        ______
        N_____________________________\ NOR \
        | _____ __| D O----N circuit
        |__/\/\_______\ NOR\ | /_____/
        R1 |____| C O---
        _|_ /____/
        C1 ___
        |
        gnd

        Now add the AVR OR gate to this circuit.
        ______
        N___________________________\ NOR \ ______ ______
        | _____ __| D O--------\ NOR \ __\ NOR \
        |_/\/\______\ NOR\ | /_____/ AVR___| A O--|__| B O---OUT
        R1 |___| C O--- /_____/ /_____/
        _|_ /____/
        C1 ___
        |
        gnd

        The whole thing is done with one quad NOR gate, 1 resistor, and 1 capacitor.

        --
        A good scientist is a person with original ideas. A good engineer is
        a person who makes a design that works with as few original ideas as
        possible. There are no prima donnas in engineering. -- Freeman Dyson

        --
        Lee A. Hart, http://www.sunrise-ev.com/LeesEVs.htm

      • joshbensadon
        Hi Bill, Ascii art doesn t come through very well for me either. Blanks are being stripped. But, what I do, is choose the Reply via Web Post at the bottom
        Message 3 of 13 , Jun 23, 2013
        • 0 Attachment
          Hi Bill,

          Ascii art doesn't come through very well for me either. Blanks are being stripped.

          But, what I do, is choose the "Reply via Web Post" at the bottom of the email. For some reason, the ascii art shows nicely on the quoted reply text.

          I captured that and will email you a text, see if you can view that.

          :)J



          --- In cosmacelf@yahoogroups.com, bill rowe <bill_rowe_ottawa@...> wrote:
          >
          > Thanks lee. Sadly I have never been able to read an ascii art message on the board or from outlook. What I get using courier shows below. I'm guessing something is stripping blanks or tabs from the beginning of lines?
          >
          >
          >
          >
          > To: cosmacelf@yahoogroups.com
          > From: leeahart@...
          > Date: Sat, 22 Jun 2013 17:38:53 -0500
          > Subject: Re: [cosmacelf] I thought this would be easy but... - logic signal combination
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          >
          > On 6/22/2013 1:33 PM, bill rowe wrote:
          >
          > >
          >
          > >
          >
          > > I have a parallel-in-serial-out shift register(CD4021) that triggers on
          >
          > > a positive edge. it's currently used by the avr microprocessor on the
          >
          > > olduino board to read the data bus. Once the register is loaded, the avr
          >
          > > can read bit 8 right away, then it toggles the clock signal, reads bit
          >
          > > 7, etc. I want the 1802 to also be able to trigger the shift register on
          >
          > > the trailing edge of N1 - it needs to be the trailing edge so a
          >
          > > peripheral can read it on the leading edge. I've drawn the two cases below
          >
          > >
          >
          > > The N line pulses are maybe 3 microseconds long, the avr's probably
          >
          > > shorter but they could be whatever I want.
          >
          > >
          >
          > > I guess I don't really care what happens at the xx point so the output
          >
          > > could stay high but not forever because sooner or later the avr would
          >
          > > want to clock it.
          >
          > >
          >
          > > Could I use a one-shot? a flip-flop? I'm stabbing in the dark here. I
          >
          > > could have the AVR assert a separate control line when it wants to clock
          >
          > > but adding another signal doesn't seem like a good idea. The AVR could
          >
          > > invert it's signal though, or anything else that seemed to help.
          >
          > >
          >
          > > Oh, I don't care if the avr's pulse gets delayed as long as I know about
          >
          > > it so that's like an OR of the two signals with a multi-us delay.
          >
          > >
          >
          > > Any help gratefully accepted. I have been chewing on this a while!
          >
          >
          >
          > I suppose there a dozen ways to do it. A lot depends on what your
          >
          > definition of a "good" solution is. My thought pattern is something like
          >
          > this:
          >
          >
          >
          > AVR is the same as OUT, so all you need between them is an OR gate.
          >
          > ______
          >
          > N circuit___\ \
          >
          > AVR___| OR O----OUT
          >
          > /_____/
          >
          >
          >
          > OR gates are less common than NOR gates. But gates come in packages of
          >
          > 4, so we have 3 extra gates for "free". We can use one section as an
          >
          > inverter. Now we have:
          >
          > ______ ______
          >
          > N circuit___\ NOR \ __\ NOR \
          >
          > AVR___| A O---|__| B O----OUT
          >
          > /_____/ /_____/
          >
          >
          >
          > N from the 1802 is delayed; so you need a one-shot (or equivalent). It
          >
          > needs to trigger on the falling edge of N, generate a positive pulse,
          >
          > and turn itself back off without any other signals.
          >
          >
          >
          > We still have 2 sections of that NOR gate. We can use an RC delay
          >
          > network to make a delayed version of N. Then combine them with a gate,
          >
          > so that OUT is only high when N is low AND delayed N is still high.
          >
          >
          >
          > 1802 N signal__--------________
          >
          > RC delayed N ______--------____
          >
          > OUT signal __________----____
          >
          >
          >
          > You already need an OR gate, and they come in packages of 4. Note that
          >
          > OUT is high when N is low; so we also need an inverter. So use this circuit:
          >
          > ______
          >
          > N_____________________________\ NOR \
          >
          > | _____ __| D O----N circuit
          >
          > |__/\/\_______\ NOR\ | /_____/
          >
          > R1 |____| C O---
          >
          > _|_ /____/
          >
          > C1 ___
          >
          > |
          >
          > gnd
          >
          >
          >
          > Now add the AVR OR gate to this circuit.
          >
          > ______
          >
          > N___________________________\ NOR \ ______ ______
          >
          > | _____ __| D O--------\ NOR \ __\ NOR \
          >
          > |_/\/\______\ NOR\ | /_____/ AVR___| A O--|__| B O---OUT
          >
          > R1 |___| C O--- /_____/ /_____/
          >
          > _|_ /____/
          >
          > C1 ___
          >
          > |
          >
          > gnd
          >
          >
          >
          > The whole thing is done with one quad NOR gate, 1 resistor, and 1 capacitor.
          >
          >
          >
          > --
          >
          > A good scientist is a person with original ideas. A good engineer is
          >
          > a person who makes a design that works with as few original ideas as
          >
          > possible. There are no prima donnas in engineering. -- Freeman Dyson
          >
          >
          >
          > --
          >
          > Lee A. Hart, http://www.sunrise-ev.com/LeesEVs.htm
          >
        • bill rowe
          excellent josh - way to teach a man to fish ! the reply via web post works great for me too. To: cosmacelf@yahoogroups.com From: joshbensadon@yahoo.com Date:
          Message 4 of 13 , Jun 23, 2013
          • 0 Attachment
            excellent josh - way to "teach a man to fish"!

            the reply via web post works great for me too.

            To: cosmacelf@yahoogroups.com
            From: joshbensadon@...
            Date: Sun, 23 Jun 2013 14:41:31 +0000
            Subject: [cosmacelf] Re: I thought this would be easy but... - logic signal combination

             
            Hi Bill,

            Ascii art doesn't come through very well for me either. Blanks are being stripped.

            But, what I do, is choose the "Reply via Web Post" at the bottom of the email. For some reason, the ascii art shows nicely on the quoted reply text.

            I captured that and will email you a text, see if you can view that.

            :)J

            --- In cosmacelf@yahoogroups.com, bill rowe <bill_rowe_ottawa@...> wrote:
            >
            > Thanks lee. Sadly I have never been able to read an ascii art message on the board or from outlook. What I get using courier shows below. I'm guessing something is stripping blanks or tabs from the beginning of lines?
            >
            >
            >
            >
            > To: cosmacelf@yahoogroups.com
            > From: leeahart@...
            > Date: Sat, 22 Jun 2013 17:38:53 -0500
            > Subject: Re: [cosmacelf] I thought this would be easy but... - logic signal combination
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            >
            > On 6/22/2013 1:33 PM, bill rowe wrote:
            >
            > >
            >
            > >
            >
            > > I have a parallel-in-serial-out shift register(CD4021) that triggers on
            >
            > > a positive edge. it's currently used by the avr microprocessor on the
            >
            > > olduino board to read the data bus. Once the register is loaded, the avr
            >
            > > can read bit 8 right away, then it toggles the clock signal, reads bit
            >
            > > 7, etc. I want the 1802 to also be able to trigger the shift register on
            >
            > > the trailing edge of N1 - it needs to be the trailing edge so a
            >
            > > peripheral can read it on the leading edge. I've drawn the two cases below
            >
            > >
            >
            > > The N line pulses are maybe 3 microseconds long, the avr's probably
            >
            > > shorter but they could be whatever I want.
            >
            > >
            >
            > > I guess I don't really care what happens at the xx point so the output
            >
            > > could stay high but not forever because sooner or later the avr would
            >
            > > want to clock it.
            >
            > >
            >
            > > Could I use a one-shot? a flip-flop? I'm stabbing in the dark here. I
            >
            > > could have the AVR assert a separate control line when it wants to clock
            >
            > > but adding another signal doesn't seem like a good idea. The AVR could
            >
            > > invert it's signal though, or anything else that seemed to help.
            >
            > >
            >
            > > Oh, I don't care if the avr's pulse gets delayed as long as I know about
            >
            > > it so that's like an OR of the two signals with a multi-us delay.
            >
            > >
            >
            > > Any help gratefully accepted. I have been chewing on this a while!
            >
            >
            >
            > I suppose there a dozen ways to do it. A lot depends on what your
            >
            > definition of a "good" solution is. My thought pattern is something like
            >
            > this:
            >
            >
            >
            > AVR is the same as OUT, so all you need between them is an OR gate.
            >
            > ______
            >
            > N circuit___\ \
            >
            > AVR___| OR O----OUT
            >
            > /_____/
            >
            >
            >
            > OR gates are less common than NOR gates. But gates come in packages of
            >
            > 4, so we have 3 extra gates for "free". We can use one section as an
            >
            > inverter. Now we have:
            >
            > ______ ______
            >
            > N circuit___\ NOR \ __\ NOR \
            >
            > AVR___| A O---|__| B O----OUT
            >
            > /_____/ /_____/
            >
            >
            >
            > N from the 1802 is delayed; so you need a one-shot (or equivalent). It
            >
            > needs to trigger on the falling edge of N, generate a positive pulse,
            >
            > and turn itself back off without any other signals.
            >
            >
            >
            > We still have 2 sections of that NOR gate. We can use an RC delay
            >
            > network to make a delayed version of N. Then combine them with a gate,
            >
            > so that OUT is only high when N is low AND delayed N is still high.
            >
            >
            >
            > 1802 N signal__--------________
            >
            > RC delayed N ______--------____
            >
            > OUT signal __________----____
            >
            >
            >
            > You already need an OR gate, and they come in packages of 4. Note that
            >
            > OUT is high when N is low; so we also need an inverter. So use this circuit:
            >
            > ______
            >
            > N_____________________________\ NOR \
            >
            > | _____ __| D O----N circuit
            >
            > |__/\/\_______\ NOR\ | /_____/
            >
            > R1 |____| C O---
            >
            > _|_ /____/
            >
            > C1 ___
            >
            > |
            >
            > gnd
            >
            >
            >
            > Now add the AVR OR gate to this circuit.
            >
            > ______
            >
            > N___________________________\ NOR \ ______ ______
            >
            > | _____ __| D O--------\ NOR \ __\ NOR \
            >
            > |_/\/\______\ NOR\ | /_____/ AVR___| A O--|__| B O---OUT
            >
            > R1 |___| C O--- /_____/ /_____/
            >
            > _|_ /____/
            >
            > C1 ___
            >
            > |
            >
            > gnd
            >
            >
            >
            > The whole thing is done with one quad NOR gate, 1 resistor, and 1 capacitor.
            >
            >
            >
            > --
            >
            > A good scientist is a person with original ideas. A good engineer is
            >
            > a person who makes a design that works with as few original ideas as
            >
            > possible. There are no prima donnas in engineering. -- Freeman Dyson
            >
            >
            >
            > --
            >
            > Lee A. Hart, http://www.sunrise-ev.com/LeesEVs.htm
            >


          • bill_rowe@rogers.com
            that looks perfect!
            Message 5 of 13 , Jun 23, 2013
            • 0 Attachment
              that looks perfect!

              --- In cosmacelf@yahoogroups.com, Lee Hart <leeahart@...> wrote:
              >
              > On 6/22/2013 1:33 PM, bill rowe wrote:
              > >
              > >
              > > I have a parallel-in-serial-out shift register(CD4021) that triggers on
              > > a positive edge. it's currently used by the avr microprocessor on the
              > > olduino board to read the data bus. Once the register is loaded, the avr
              > > can read bit 8 right away, then it toggles the clock signal, reads bit
              > > 7, etc. I want the 1802 to also be able to trigger the shift register on
              > > the trailing edge of N1 - it needs to be the trailing edge so a
              > > peripheral can read it on the leading edge. I've drawn the two cases below
              > >
              > > The N line pulses are maybe 3 microseconds long, the avr's probably
              > > shorter but they could be whatever I want.
              > >
              > > I guess I don't really care what happens at the xx point so the output
              > > could stay high but not forever because sooner or later the avr would
              > > want to clock it.
              > >
              > > Could I use a one-shot? a flip-flop? I'm stabbing in the dark here. I
              > > could have the AVR assert a separate control line when it wants to clock
              > > but adding another signal doesn't seem like a good idea. The AVR could
              > > invert it's signal though, or anything else that seemed to help.
              > >
              > > Oh, I don't care if the avr's pulse gets delayed as long as I know about
              > > it so that's like an OR of the two signals with a multi-us delay.
              > >
              > > Any help gratefully accepted. I have been chewing on this a while!
              >
              > I suppose there a dozen ways to do it. A lot depends on what your
              > definition of a "good" solution is. My thought pattern is something like
              > this:
              >
              > AVR is the same as OUT, so all you need between them is an OR gate.
              > ______
              > N circuit___\ \
              > AVR___| OR O----OUT
              > /_____/
              >
              > OR gates are less common than NOR gates. But gates come in packages of
              > 4, so we have 3 extra gates for "free". We can use one section as an
              > inverter. Now we have:
              > ______ ______
              > N circuit___\ NOR \ __\ NOR \
              > AVR___| A O---|__| B O----OUT
              > /_____/ /_____/
              >
              > N from the 1802 is delayed; so you need a one-shot (or equivalent). It
              > needs to trigger on the falling edge of N, generate a positive pulse,
              > and turn itself back off without any other signals.
              >
              > We still have 2 sections of that NOR gate. We can use an RC delay
              > network to make a delayed version of N. Then combine them with a gate,
              > so that OUT is only high when N is low AND delayed N is still high.
              >
              > 1802 N signal__--------________
              > RC delayed N ______--------____
              > OUT signal __________----____
              >
              > You already need an OR gate, and they come in packages of 4. Note that
              > OUT is high when N is low; so we also need an inverter. So use this circuit:
              > ______
              > N_____________________________\ NOR \
              > | _____ __| D O----N circuit
              > |__/\/\_______\ NOR\ | /_____/
              > R1 |____| C O---
              > _|_ /____/
              > C1 ___
              > |
              > gnd
              >
              > Now add the AVR OR gate to this circuit.
              > ______
              > N___________________________\ NOR \ ______ ______
              > | _____ __| D O--------\ NOR \ __\ NOR \
              > |_/\/\______\ NOR\ | /_____/ AVR___| A O--|__| B O---OUT
              > R1 |___| C O--- /_____/ /_____/
              > _|_ /____/
              > C1 ___
              > |
              > gnd
              >
              > The whole thing is done with one quad NOR gate, 1 resistor, and 1 capacitor.
              >
              > --
              > A good scientist is a person with original ideas. A good engineer is
              > a person who makes a design that works with as few original ideas as
              > possible. There are no prima donnas in engineering. -- Freeman Dyson
              >
              > --
              > Lee A. Hart, http://www.sunrise-ev.com/LeesEVs.htm
              >
            • Lee Hart
              ... Looks like something is replacing all occurrences of more than one space with a single space. When I view my message online at
              Message 6 of 13 , Jun 23, 2013
              • 0 Attachment
                On 6/23/2013 6:59 AM, bill rowe wrote:
                > Thanks lee. Sadly I have never been able to read an ascii art message on
                > the board or from outlook. What I get using courier shows below. I'm
                > guessing something is stripping blanks or tabs from the beginning of lines?

                Looks like something is replacing all occurrences of more than one space
                with a single space.

                When I view my message online at
                http://groups.yahoo.com/group/cosmacelf/messages, all the spaces are
                intact and the circuit appears as I sent it. So the message is making it
                onto Yahoo intact.

                Here are the same four illustrations, but with periods in place of
                spaces. Does that work better?

                ............______.........
                N circuit___\.....\........
                ..... AVR___| OR . O----OUT
                ............/_____/........
                ...........................

                ............______........______.........
                N circuit___\ NOR \.....__\ NOR \........
                ..... AVR___|. A . O---|__|. B . O----OUT
                ............/_____/......./_____/........
                .........................................

                .............................._____................
                N_____________________________\ NOR \..............
                ...|............._____......__|. D . O----N circuit
                ...|__/\/\_______\ NOR\....|../_____/..............
                ...... R1 ..|____|. C .O---........................
                ..........._|_.../____/............................
                ....... C1 ___.....................................
                ............|......................................
                ...........gnd.....................................

                .......................................................................
                ............................______.....................................
                N___________________________\ NOR \.........______.......______........
                ...|..........._____......__|. D . O--------\ NOR \....__\ NOR \.......
                ...|_/\/\______\ NOR\....|../_____/.. AVR___|. A . O--|__|. B . O---OUT
                ..... R1 ..|___|. C .O---.................../_____/....../_____/.......
                .........._|_../____/..................................................
                ...... C1 ___..........................................................
                ...........|...........................................................
                ..........gnd..........................................................
                --
                Results! Why man, I have gotten a lot of results. I know several
                thousand things that won't work. -- Thomas A. Edison
                --
                Lee A. Hart, http://www.sunrise-ev.com/LeesEVs.htm
              • Josh Bensadon
                Lee, The dots work well! I guess the problem is with Yahoo sending out the email. I would like to say an 8 bit ELF computer would never strip spaces, but
                Message 7 of 13 , Jun 23, 2013
                • 0 Attachment
                  Lee,

                  The dots work well!

                  I guess the problem is with Yahoo sending out the email.
                  I would like to say an 8 bit ELF computer would never strip spaces, but that's just not true. You'll find on some of my monitors that I strip white space because it shouldn't matter if you type "D 0000" or "D 0000".

                  :)J


                  --- On Sun, 6/23/13, Lee Hart <leeahart@...> wrote:

                  > From: Lee Hart <leeahart@...>
                  > Subject: Re: [cosmacelf] I thought this would be easy but... - logic signal combination
                  > To: cosmacelf@yahoogroups.com
                  > Received: Sunday, June 23, 2013, 9:56 AM
                  > On 6/23/2013 6:59 AM, bill rowe
                  > wrote:
                  > > Thanks lee. Sadly I have never been able to read an
                  > ascii art message on
                  > > the board or from outlook. What I get using courier
                  > shows below. I'm
                  > > guessing something is stripping blanks or tabs from the
                  > beginning of lines?
                  >
                  > Looks like something is replacing all occurrences of more
                  > than one space
                  > with a single space.
                  >
                  > When I view my message online at
                  > http://groups.yahoo.com/group/cosmacelf/messages, all
                  > the spaces are
                  > intact and the circuit appears as I sent it. So the message
                  > is making it
                  > onto Yahoo intact.
                  >
                  > Here are the same four illustrations, but with periods in
                  > place of
                  > spaces. Does that work better?
                  >
                  > ............______.........
                  > N circuit___\.....\........
                  > ..... AVR___| OR . O----OUT
                  > ............/_____/........
                  > ...........................
                  >
                  > ............______........______.........
                  > N circuit___\ NOR \.....__\ NOR \........
                  > ..... AVR___|. A . O---|__|. B . O----OUT
                  > ............/_____/......./_____/........
                  > .........................................
                  >
                  > .............................._____................
                  > N_____________________________\ NOR \..............
                  > ...|............._____......__|. D . O----N circuit
                  > ...|__/\/\_______\ NOR\....|../_____/..............
                  > ...... R1 ..|____|. C .O---........................
                  > ..........._|_.../____/............................
                  > ....... C1 ___.....................................
                  > ............|......................................
                  > ...........gnd.....................................
                  >
                  > .......................................................................
                  > ............................______.....................................
                  > N___________________________\ NOR
                  > \.........______.......______........
                  > ...|..........._____......__|. D . O--------\ NOR \....__\
                  > NOR \.......
                  > ...|_/\/\______\ NOR\....|../_____/.. AVR___|. A . O--|__|.
                  > B . O---OUT
                  > ..... R1 ..|___|. C
                  > .O---.................../_____/....../_____/.......
                  > .........._|_../____/..................................................
                  > ...... C1
                  > ___..........................................................
                  > ...........|...........................................................
                  > ..........gnd..........................................................
                  > --
                  > Results! Why man, I have gotten a lot of results. I know
                  > several
                  > thousand things that won't work. -- Thomas A. Edison
                  > --
                  > Lee A. Hart, http://www.sunrise-ev.com/LeesEVs.htm
                  >
                  >
                  > ------------------------------------
                  >
                  > ========================================================
                  > Questions? Check the FAQ at http://www.cosmacelf.com/forumfaq.html
                  > Visit the COSMAC ELF website at http://www.cosmacelf.comYahoo! Groups Links
                  >
                  >
                  >     cosmacelf-fullfeatured@yahoogroups.com
                  >
                  >
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