16-bit 1802 hybrid?
- I've been noodling around an idea for running two 1802 chips as quasi-parallel processors where one is dedicated to the upper byte of 16-bit operations and the other to the lower byte. The idea is to use the MSB processor (in most cases) to do the fetches of real 8-bit opcodes, while the LSB processor gets fed either the same or suitably altered opcodes.
As I see it, it's a matter of finding an efficient external way to keep track of what the DF value is for the LSB for instructions that can change it -- adds, subtracts, and rotates -- and then fiddling with the relative clock phases of the MSB and LSB processors so that for those DF-modifying instructions are completed in the LSB chip before allowing the MSB chip to complete the equivalent operation.
The "easiest" cases are the add and subtract instructions. The LSB performs these instructions with little or no modification, and an external DF flip-flop -- call it DFL -- acts as a carry-in to the MSB chip. Now, getting that carry bit into the MSB processor is a bit more involved.
I've considered several options, but the simplest seems to be an 8-bit presettable UP/DOWN counter with a tristate register. The counter gets the B-register add/subtract value from memory, then, depending on DFL and the instruction being executed is incremented, decremented, or left unchanged before being switched onto the MSB processor data bus, whence the MSB chip completes its execution.
Shift instructions might require as little as keeping track of the MSB and LSB bits of both D registers, provided a clever way can be thought of to sneak those values into their proper destinations to make the two D registers behave as if they are part of a 16-bit + carry bidirectional shift register.
Anyway, that's as far as I've managed to blue-sky this idea.
- I am have a sense of deja vu :-) about 2 years ago?
From: David Keith <beloved_wind@...>
To: "email@example.com" <firstname.lastname@example.org>
Sent: Sunday, April 7, 2013 8:12 PM
Subject: Re: [cosmacelf] Re: CDP1806ACE - 1802 ISA Standards Committee??
How about this group forming a 1802 Instructions Set Architecture (ISA) standards committee to agree on the expansion of the 1802 past the 1805/6 32 instructions. We could add at lease 223 more (two byte) instructions of the form 68XX.// DD
From: jdrose_8_bit <rarecoinbuyer@...>
Sent: Sunday, April 7, 2013 3:42 PM
Subject: [cosmacelf] Re: CDP1806ACE
"instructions add subroutine call and return capability"
OK, yeah, that is a pretty big addition.
--- In email@example.com, Dave Ruske <dave@...> wrote:
> 32 instructions added, see:
> From the summary on that data sheet:
> "The 32 new software instructions add subroutine call and return capability, enhanced data transfer manipulation, Counter/Timer control, improved interrupt handling, single-instruction loop counting, and BCD arithmetic."
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