Loading ...
Sorry, an error occurred while loading the content.

7778Re: Parallelf memory map

Expand Messages
  • ajparent1
    Jul 1, 2011
      --- In cosmacelf@yahoogroups.com, "Richard" <r.dienstknecht@...> wrote:
      >
      > Good morning!
      >
      > Yes, I think you are right. Up to now I had been busy coming up with a practicable concept, now it's time to write down what I have and what not. If I had not to go to work right now, I would get on it right away.
      >


      If you ponder it long enough the issue is task oriented or process oriented. In one the whole task is dedicated to a cpu and may share resources like ram, io or whatever. The other the process decomposed and serialized so that one cpu does say input stream processing, the next does some further work to the data and the third though N do more with the last outputting the results. One may dictate a configuration but the tasks at hand may not be efficiently performed with that topology.

      There are many issues to overcome locking and prioritizing the who gets what resource first when there are multiple requests. Job overlap and inter-job or inter-task communications to be resolved.
      The more flexibility you build in the greater complexity and debugging.

      I've done this on S100 bus with Z80s and it was fun, enlightening
      and loads of work. But the end result was not faster by much.

      An alternate approach is build a 1802 in TTL (or fast CMOS) and run at 20mhz or faster. As CPUs go the 1802 is one of the simplest
      and going faster has it's potential when you consider most run
      it at sub 3mhz. This has been done for many other classic cpus but 1802 has not been to my knowledge done. I've pondered it but every time I find myself wondering down the road to a stretched 16 or 32bit variant with byte oriented bus and instructions.


      Allison
    • Show all 10 messages in this topic