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61244Re: [beam] Memristor

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  • Richard Piotter
    Dec 24, 2013
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      The decay line is a low pulse rate that increments the weight registers to "forget" their conditioning. The pulse must be slow enough to allow for an equilibrium between active input activity and low input activity. It can be sourced by sensory or other neuronal outputs, or it could just be a very slow (compared to typical neuronal activity) global pulse.

      It's meant to represent time in the digital neuron. Since it uses asynchronous clocking derived by either propagation delay of the inputs, or by sampling inputs for highs and lows (based on configuration), there is no clear means to represent time as a function of de-conditioning, or forgetfulness. The decay line allows this to be loosely emulated. Every time the neuron fires, it takes one less cumulative excitatory pulse to fire the nest time. The first time the neuron fires, it would take 32 input pulses to trigger it. the next time, it takes 31 pulses, then 30, 29, 28, and so on, till it reaches a 1 to 1 input pulse to output fire ratio. The decay line increases the number of input pulses required for it to fire by one pulse increment with every trigger of the decay line.

      It's horribly low resolution, and very crude means to create a neuron, but the fact you can fit multiple neurons on even Xilinx's smallest 9536 CPLD, a $7 chip, is where the apparent appeal lies, in my opinion. Nv and Nu circuits are very nice, but there is a clear lack of adaptability in the area of neuron approximation. Yeah, you can have a sensor or logic tie different resistor values into an Nv circuit, but it really isn't much like neurons. There isn't a lot of asynchronous pulse streams that represent analog outputs in BEAM... It's mostly linear pulse trains and pulse length/order modification.

      I don't know that many people would use this type of digital neuron in their circuits, or that it'd be easy to get it to actually do anything, but I feel like it would be nice for it to actually exist, incase someone actually does want to play with it! :)

      This is a VERY crude block diagram of the neuron. Sadly, I seem to have lost the logic level schematic, and am looking for it. It's a simple enough design, that I should be able to easily redo it from scratch, should I get the time.


      I'll be busy pretty much all week, so i may not get to it till later, but I have more pics of the memristor progress... Though as I stated earlier, I seem to have had a low success rate... I honestly don't even know if the silver based circuit pen traces will work in place of aluminum.

      Richard Piotter

      Begin forwarded message:
      > From: <connor_ramsey@...>
      > Subject: Re: [beam] Memristor
      > Date: December 23, 2013 11:18:50 PM CST
      > To: <beam@yahoogroups.com>
      > Reply-To: beam@yahoogroups.com
      > For now I'm just going to assume that the decay line in the Xilinx neuron you described connects like the other two synapses. Which I just figured out how I'm going to connect all of the neurons in my ZISC computer.
      > If I used a ROM matrix to coordinate all of the synaptic connections either in series or parallel, I need 3n^2 bits of ROM, where n = neuron count. Not a problem for small networks, but say I have 256 neurons to account for, and that makes 576KbB of ROM. Granted that's not nearly a lot at first glance, but that's just with 8bit addresses. When you get to 32 bits, that's 147,456 TbBs! No way that's happening!
      > So Instead, I going to use a PAL as the "synapse memory", where whenever a neuron fires, it outputs its address number, which is fed into the PAL, and then the pulse is sent to every other address that has the neuron's address as one of its terms. Basically the communication between neurons will work by processing the neurons with the lowest weight values first, and more decayed neurons last. Neurons with equal weights are processed in numerical order. I'm still working out the logic for this process, as I'm working on the computer right now, out of impulse.
      > But anyway, this way, for the same 100 neurons, only 40 bytes of synapse memory are required, and for 2^32 neurons, that's only 64MbBs for the synapse connections, and 16MbBs in total weight memory(assuming 32bit neurons).
      > Anyway, enjoy, Connor
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