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54699Re: Hexapod Update - testing

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  • Joseph Charles
    Dec 1, 2006
      Hi Wilf,

      Thanks for that. I've moved the chips around a bit, but still no luck.
      I may have a go at building the circuit on some perfboard to see if
      that makes a difference. All depends on available time!

      Thanks again for the explanation.



      --- In beam@yahoogroups.com, "wilf_nv" <wrigter@...> wrote:
      > Hi Jo,
      > Probably only occurs on the bread board with the larger stray
      > capacitance between contacts.
      > The second resistor in series with the inverter input together with
      > the stray input capcitance acts like a small RC filter that can slow
      > the rise and fall times of the input waveform long enough to permit
      > double transitions in the output waveform during switching. These
      > double transistions are divided by the FF with the result that the
      > FF output seems to follow the clock input.
      > Lowering the value of the series resistor to the minimum that will
      > still generate 50% dutycycle, will reduce the likelyhood of the
      > double transitions
      > Another way to test if this is a breadboard issue is to use a
      > different layout of inverters with corresponding different stray
      > capacitive coupling.
      > wilf
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