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Re: HET will not go into counter interrupt, but instead, resets my I/O & vars.

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  • wickdastic
    I came across something similar while debugging my code. The default tms470r1b1m_low_level_init_flash.c from IAR and/or TI includes the line: SYSECR = RESET0
    Message 1 of 4 , Jun 23, 2008
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      I came across something similar while debugging my code. The default
      tms470r1b1m_low_level_init_flash.c from IAR and/or TI includes the line:

      SYSECR = RESET0 + PACCOVR + ACCOVR + ILLOVR;

      This causes the debugger to ignore ARM core violations when the ~TRST
      pin is active! The Segger j-link debugger will set TRST low when
      connected and debugging. You may want to try commenting out this line
      and see if you are causing an access violation of some kind. See the
      SYSECR register description in the System Module Reference Guide for
      more info.

      Regards, Tom
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