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DMA and SPI for TMS470

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  • michaguenther
    Hello news group, actualy I try out the DMA on the TMS470 1M version. The problem is to write music data from internal flash memory to en external mp3-decoder
    Message 1 of 4 , Dec 29, 2007
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      Hello news group,

      actualy I try out the DMA on the TMS470 1M version. The problem is to
      write music data from internal flash memory to en external mp3-decoder
      via spi. i like to use the dma and I connected the DataRequest signal
      from the mp3-decoder chip to the spi-enable pin of the tms470. The i
      feed the mp3-decoder chip with a data stream via spi and if the chip
      has enough datas, it stops the dma transfer (wait...) by rising the
      spi-enable line low. if the internal decode process in the decoderchip
      was done, the decoder chip sets the DataReq line high, so the DMA goes
      on its data sending.

      Well, the following situation I use:

      1. I use an array of near 64 kBytes of data as a const array and
      included it in my code headerfile:

      const unsigned char musik[];

      2. Then i configure the mp3-decoder chip via i2c (that works fine) and
      after that I configure the DMA:

      void InitDMA_STA013(void)
      {
      DMAC = rDMAC;
      DMASA = (int)&musik[0];
      DMADA = 0xFFF7F80C;
      DMATC = 0xffff;
      DMACC0 = 0x00000a00;
      DMAGC = 0x00000000;
      DMAGD = 0x00000000;
      DMAS &= ~(IF2 | TC);
      }

      with rDMA is:

      #define NCPACK (0x00 << 24) // next packet
      #define INTEN (1 << 15) // interrupt after compleate
      #define TRSIZE (0 << 13) // transfer access size
      #define DSTINC (0 << 11) // dest address increment
      #define SRCINC (1 << 9) // source address increment
      #define DSTMOD (0xF << 5) // dest module
      #define SRCMOD (0x1 << 1) // source module
      #define DCHN (0 << 0) // Data chaining enable

      #define rDMAC (0x00000000 | NCPACK | INTEN | TRSIZE | DSTINC | SRCINC
      | DSTMOD | SRCMOD | DCHN)

      3. After the DMA init I start the DMA:

      DMACPS = 0x00000001; //update for transfer
      DMACCP0 = DMA_EN2; //enable the DMA to transfer

      Well, this works fine for one cycle (64kByte of data) and an dma
      interrupt occour. but if I restart the code running from begĂ­nning or
      I stop the dma while it runs, I can not restart the system. The
      debugger goes to undefined code addresses. If I power of my board
      (disconnect the power supply AND the olimex JTAG pod), wait some
      seconds and conect it together and then start the apps again, it
      works. But for only one cycle.....

      Is there a missing "flag" I should set or reset, afterreaching the dma
      end???

      Please help,
      Micha.
    • JohnStosh
      I ll be doing DMA, like Micha; but I ll be doing DMA out to an SCI port on the TMS470. I m actually using the tms470r1b1m. Does anyone have any example code
      Message 2 of 4 , Jan 12, 2008
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        I'll be doing DMA, like Micha; but I'll be doing DMA out to an SCI port on the TMS470.  I'm actually using the tms470r1b1m.  Does anyone have any example code of DMA working for anything?
        -John


        ----- Original Message ----
        From: michaguenther <mguenther080777@...>
        To: TMS470_ARM@yahoogroups.com
        Sent: Saturday, December 29, 2007 2:27:11 PM
        Subject: [TMS470_ARM] DMA and SPI for TMS470

        Hello news group,

        actualy I try out the DMA on the TMS470 1M version. The problem is to
        write music data from internal flash memory to en external mp3-decoder
        via spi. i like to use the dma and I connected the DataRequest signal
        from the mp3-decoder chip to the spi-enable pin of the tms470. The i
        feed the mp3-decoder chip with a data stream via spi and if the chip
        has enough datas, it stops the dma transfer (wait...) by rising the
        spi-enable line low. if the internal decode process in the decoderchip
        was done, the decoder chip sets the DataReq line high, so the DMA goes
        on its data sending.

        Well, the following situation I use:

        1. I use an array of near 64 kBytes of data as a const array and
        included it in my code headerfile:

        const unsigned char musik[];

        2. Then i configure the mp3-decoder chip via i2c (that works fine) and
        after that I configure the DMA:

        void InitDMA_STA013( void)
        {
        DMAC = rDMAC;
        DMASA = (int)&musik[ 0];
        DMADA = 0xFFF7F80C;
        DMATC = 0xffff;
        DMACC0 = 0x00000a00;
        DMAGC = 0x00000000;
        DMAGD = 0x00000000;
        DMAS &= ~(IF2 | TC);
        }

        with rDMA is:

        #define NCPACK (0x00 << 24) // next packet
        #define INTEN (1 << 15) // interrupt after compleate
        #define TRSIZE (0 << 13) // transfer access size
        #define DSTINC (0 << 11) // dest address increment
        #define SRCINC (1 << 9) // source address increment
        #define DSTMOD (0xF << 5) // dest module
        #define SRCMOD (0x1 << 1) // source module
        #define DCHN (0 << 0) // Data chaining enable

        #define rDMAC (0x00000000 | NCPACK | INTEN | TRSIZE | DSTINC | SRCINC
        | DSTMOD | SRCMOD | DCHN)

        3. After the DMA init I start the DMA:

        DMACPS = 0x00000001; //update for transfer
        DMACCP0 = DMA_EN2; //enable the DMA to transfer

        Well, this works fine for one cycle (64kByte of data) and an dma
        interrupt occour. but if I restart the code running from begĂ­nning or
        I stop the dma while it runs, I can not restart the system. The
        debugger goes to undefined code addresses. If I power of my board
        (disconnect the power supply AND the olimex JTAG pod), wait some
        seconds and conect it together and then start the apps again, it
        works. But for only one cycle.....

        Is there a missing "flag" I should set or reset, afterreaching the dma
        end???

        Please help,
        Micha.




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      • marjan_hanc
        Hi, there is not much help recently on this forum, so for the newbies, I would not recommend this CPU to use in their design. Documentation is fuzzy and in
        Message 3 of 4 , Jan 14, 2008
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          Hi,

          there is not much help recently on this forum, so for the newbies,
          I would not recommend this CPU to use in their design. Documentation
          is fuzzy and in some parts incomplete, TI support sucks ;-(

          Still, here is the example excerpt from my code running DMA
          communication over SCI1 you might find useful. See comments below.

          void SCI_INIT()
          {
          // Initialize SCI1


          SCI1CTL3 &= ~SW_NRESET; // Reset SCI
          SCI1CCR = 0x17; // Async, 8-bit
          SCI1CTL1 |= RXENA + RX_DMA_ENA + RX_DMA_ALL;
          SCI1CTL2 |= TXENA + TX_DMA_ENA;
          SCI1CTL3 |= CLOCK + RX_ACTION_ENA + TX_ACTION_ENA + RXERR_INT_ENA;

          SCI1LBAUD = 20; // (115200bps @ 14.477MHz sysclk)

          SCI1PC2 |= RX_FUNC;
          SCI1PC3 |= TX_FUNC;
          SCI1CTL3 |= SW_NRESET;
          }

          void DMA_RX_INIT(unsigned short msglen)

          // DMA Control RX packet definitions for SCI0

          DMAC00 = TRSIZE_0 + DSTINC + DSTMOD_2 + SRCMOD_15;
          // NCPACK=0
          DMASA00 = (unsigned long)&SCI1RXBUF;
          DMADA00 = (unsigned long)&rxbuffer;
          DMATC00 = (unsigned short)msglen;

          // DMA channel initialization

          DMACC0 |= SEN4 + RQEN4;

          // DMA global registers initialization

          DMAGC = 0;
          DMAGD = 0;
          DMACPS |= RX_DMA_SCI0; // Control packet 0
          DMACCP1 |= DMEN4;
          }


          First the call is made to DMA_RX_INIT in order to receive the packet
          of the given size (msglen) in the rxbuffer (array of char).

          Receiving is done asynch. in main() by checking (DMACPS & RX_DMA_SCI0)==0)

          Once we receive the packet, transmitting goes similar...

          void DMA_SEND_TX(unsigned short bytecnt)
          {
          // DMA Control TX packet for SCI0 definitions

          DMAC01 = NCPACK_1 + TRSIZE_0 + SRCINC + SRCMOD_2 + DSTMOD_15;
          DMASA01 = (unsigned long)&txbuff;
          DMADA01 = (unsigned long)&SCI1TXBUF;
          DMATC01 = (unsigned short)bytecnt;

          // DMA channel initialization

          DMACC0 |= SEN5 + RQEN5;

          // DMA global registers initialization

          DMAGC = 0;
          DMAGD = 0;
          DMACPS |= TX_DMA_SCI0; // Control packet 1
          DMACCP1 |= DMEN5 + CCPACK5_1;
          }

          Transmit end is checked asynchronous in the main() similar as for the
          RX, by checking if (DMACPS & TX_DMA_SCI0)==0.

          If the design allows, you might use IRQ to check DMA RX/TX end.

          Hope it helps.

          Best regards,
          Marjan
        • JohnStosh
          This should give me a start. Thanks ever so much. ... From: marjan_hanc To: TMS470_ARM@yahoogroups.com Sent: Monday, January 14, 2008
          Message 4 of 4 , Jan 18, 2008
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            This should give me a start.  Thanks ever so much.

            ----- Original Message ----
            From: marjan_hanc <marjan.hanc@...>
            To: TMS470_ARM@yahoogroups.com
            Sent: Monday, January 14, 2008 11:19:19 AM
            Subject: [TMS470_ARM] Re: DMA and SPI for TMS470

            Hi,

            there is not much help recently on this forum, so for the newbies,
            I would not recommend this CPU to use in their design. Documentation
            is fuzzy and in some parts incomplete, TI support sucks ;-(

            Still, here is the example excerpt from my code running DMA
            communication over SCI1 you might find useful. See comments below.

            void SCI_INIT()
            {
            // Initialize SCI1


            SCI1CTL3 &= ~SW_NRESET; // Reset SCI
            SCI1CCR = 0x17; // Async, 8-bit
            SCI1CTL1 |= RXENA + RX_DMA_ENA + RX_DMA_ALL;
            SCI1CTL2 |= TXENA + TX_DMA_ENA;
            SCI1CTL3 |= CLOCK + RX_ACTION_ENA + TX_ACTION_ENA + RXERR_INT_ENA;

            SCI1LBAUD = 20; // (115200bps @ 14.477MHz sysclk)

            SCI1PC2 |= RX_FUNC;
            SCI1PC3 |= TX_FUNC;
            SCI1CTL3 |= SW_NRESET;
            }

            void DMA_RX_INIT( unsigned short msglen)

            // DMA Control RX packet definitions for SCI0

            DMAC00 = TRSIZE_0 + DSTINC + DSTMOD_2 + SRCMOD_15;
            // NCPACK=0
            DMASA00 = (unsigned long)&SCI1RXBUF;
            DMADA00 = (unsigned long)&rxbuffer;
            DMATC00 = (unsigned short)msglen;

            // DMA channel initialization

            DMACC0 |= SEN4 + RQEN4;

            // DMA global registers initialization

            DMAGC = 0;
            DMAGD = 0;
            DMACPS |= RX_DMA_SCI0; // Control packet 0
            DMACCP1 |= DMEN4;
            }

            First the call is made to DMA_RX_INIT in order to receive the packet
            of the given size (msglen) in the rxbuffer (array of char).

            Receiving is done asynch. in main() by checking (DMACPS & RX_DMA_SCI0) ==0)

            Once we receive the packet, transmitting goes similar...

            void DMA_SEND_TX( unsigned short bytecnt)
            {
            // DMA Control TX packet for SCI0 definitions

            DMAC01 = NCPACK_1 + TRSIZE_0 + SRCINC + SRCMOD_2 + DSTMOD_15;
            DMASA01 = (unsigned long)&txbuff;
            DMADA01 = (unsigned long)&SCI1TXBUF;
            DMATC01 = (unsigned short)bytecnt;

            // DMA channel initialization

            DMACC0 |= SEN5 + RQEN5;

            // DMA global registers initialization

            DMAGC = 0;
            DMAGD = 0;
            DMACPS |= TX_DMA_SCI0; // Control packet 1
            DMACCP1 |= DMEN5 + CCPACK5_1;
            }

            Transmit end is checked asynchronous in the main() similar as for the
            RX, by checking if (DMACPS & TX_DMA_SCI0) ==0.

            If the design allows, you might use IRQ to check DMA RX/TX end.

            Hope it helps.

            Best regards,
            Marjan




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