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Mapping PSoC pins with Eagle CAD

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  • Lloyd Moore
    Folks, There was a question at the end of the talk yesterday about how to map pins from the PSoC Creator design into something that Eagle CAD can consume. I
    Message 1 of 2 , Jul 17, 2011
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      Folks,

       

      There was a question at the end of the talk yesterday about how to map pins from the PSoC Creator design into something that Eagle CAD can consume. I did a quick check when I got home and the .rpt file (generated during the build) contains an HTML like section that appears as follows:

       

      <CYPRESSTAG name="Port Configuration Details">

       

      ------------------------------------------------------------

      Port Configuration report

      ------------------------------------------------------------

           |     |       | Interrupt |                  |                 |

      Port | Pin | Fixed |      Type |       Drive Mode |            Name | Connections

      -----+-----+-------+-----------+------------------+-----------------+--------------

         2 |   0 |     * |      NONE |         CMOS_OUT |      LED_LSB(0) | In(Net_78_0)

           |   1 |     * |      NONE |         CMOS_OUT |      LED_LSB(1) | In(Net_78_1)

           |   2 |     * |      NONE |         CMOS_OUT |      LED_LSB(2) | In(Net_78_2)

           |   3 |     * |      NONE |         CMOS_OUT |      LED_LSB(3) | In(Net_78_3)

      -----+-----+-------+-----------+------------------+-----------------+--------------

         3 |   5 |     * |      NONE |      HI_Z_ANALOG |   Adc_X_Axis(0) | Analog(Net_9)

      -----+-----+-------+-----------+------------------+-----------------+--------------

         4 |   0 |     * |      NONE |         CMOS_OUT |      LED_MSB(0) | In(Net_78_3)

           |   1 |     * |      NONE |         CMOS_OUT |      LED_MSB(1) | In(Net_78_4)

           |   2 |     * |      NONE |         CMOS_OUT |      LED_MSB(2) | In(Net_78_5)

           |   3 |     * |      NONE |         CMOS_OUT |      LED_MSB(3) | In(Net_78_6)

      -----+-----+-------+-----------+------------------+-----------------+--------------

        15 |   0 |     * |      NONE |         CMOS_OUT | Accl_Control(0) |

           |   1 |     * |      NONE |         CMOS_OUT | Accl_Control(1) |

           |   2 |     * |      NONE |         CMOS_OUT | Accl_Control(2) |

      -----------------------------------------------------------------------------------

      </CYPRESSTAG>

       

      Should be fairly easy to grab this out of the report file and make a converter to rename the pins on a template Eagle CAD component. There would need to be one more table that maps Port:Pin to the specific pin on the chip, but once you have that this table will map the Port:Pin to the user specified name in the design, and can also specify the mode (in/out/bidirectional) of the pin.

       

      Thanks,

      Lloyd Moore,

      President

       

         www.CyberData-Robotics.com

                     1.206.715.7628

       

       

      This electronic mail (including attachments) may contain information that is privileged, confidential, and/or otherwise protected from disclosure to anyone other than its intended recipient(s). Any dissemination or use of this electronic email or its contents (including attachments) by persons other than the intended recipient(s) is strictly prohibited. If you have received this message in error, please notify us immediately by reply email so that we may correct the situation. Please delete the original message (including attachments) in its entirety. Thank you.

       

    • Mike Payson
      Looks interesting, Lloyd. Thanks for following up!
      Message 2 of 2 , Jul 17, 2011
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        Looks interesting, Lloyd. Thanks for following up!

        On Sun, Jul 17, 2011 at 9:12 AM, Lloyd Moore <moorel3@...> wrote:


        Folks,

         

        There was a question at the end of the talk yesterday about how to map pins from the PSoC Creator design into something that Eagle CAD can consume. I did a quick check when I got home and the .rpt file (generated during the build) contains an HTML like section that appears as follows:

         

        <CYPRESSTAG name="Port Configuration Details">

         

        ------------------------------------------------------------

        Port Configuration report

        ------------------------------------------------------------

             |     |       | Interrupt |                  |                 |

        Port | Pin | Fixed |      Type |       Drive Mode |            Name | Connections

        -----+-----+-------+-----------+------------------+-----------------+--------------

           2 |   0 |     * |      NONE |         CMOS_OUT |      LED_LSB(0) | In(Net_78_0)

             |   1 |     * |      NONE |         CMOS_OUT |      LED_LSB(1) | In(Net_78_1)

             |   2 |     * |      NONE |         CMOS_OUT |      LED_LSB(2) | In(Net_78_2)

             |   3 |     * |      NONE |         CMOS_OUT |      LED_LSB(3) | In(Net_78_3)

        -----+-----+-------+-----------+------------------+-----------------+--------------

           3 |   5 |     * |      NONE |      HI_Z_ANALOG |   Adc_X_Axis(0) | Analog(Net_9)

        -----+-----+-------+-----------+------------------+-----------------+--------------

           4 |   0 |     * |      NONE |         CMOS_OUT |      LED_MSB(0) | In(Net_78_3)

             |   1 |     * |      NONE |         CMOS_OUT |      LED_MSB(1) | In(Net_78_4)

             |   2 |     * |      NONE |         CMOS_OUT |      LED_MSB(2) | In(Net_78_5)

             |   3 |     * |      NONE |         CMOS_OUT |      LED_MSB(3) | In(Net_78_6)

        -----+-----+-------+-----------+------------------+-----------------+--------------

          15 |   0 |     * |      NONE |         CMOS_OUT | Accl_Control(0) |

             |   1 |     * |      NONE |         CMOS_OUT | Accl_Control(1) |

             |   2 |     * |      NONE |         CMOS_OUT | Accl_Control(2) |

        -----------------------------------------------------------------------------------

        </CYPRESSTAG>

         

        Should be fairly easy to grab this out of the report file and make a converter to rename the pins on a template Eagle CAD component. There would need to be one more table that maps Port:Pin to the specific pin on the chip, but once you have that this table will map the Port:Pin to the user specified name in the design, and can also specify the mode (in/out/bidirectional) of the pin.

         

        Thanks,

        Lloyd Moore,

        President

         

           www.CyberData-Robotics.com

                       1.206.715.7628

         

         

        This electronic mail (including attachments) may contain information that is privileged, confidential, and/or otherwise protected from disclosure to anyone other than its intended recipient(s). Any dissemination or use of this electronic email or its contents (including attachments) by persons other than the intended recipient(s) is strictly prohibited. If you have received this message in error, please notify us immediately by reply email so that we may correct the situation. Please delete the original message (including attachments) in its entirety. Thank you.

         




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