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48168Video processing on the NeRP platform...

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  • K Maxon
    Dec 28, 2013

      While  at the SRS meeting this month I showed three of the new  CCAs that make up the video processing subsystem for the  NeRP project.

      One of the first  largeish chunks of that work is now coming online.  I thought to take a minute and share since I captured an image that really tells the  story.  The 625Mbit data pipes from the video system processor board out to the display driver board are up and running / debugged.  The FPGA video output pipe is up and running,along with the multi-ported RAM interfaces and the embedded processor video overlay functions.  Put all of this together and you get the following image.

      Needless to say,  even though I am swamped with contract work, with progress like this I am still smilin' over  the holliday season.