Loading ...
Sorry, an error occurred while loading the content.

15318Re: [SeattleRobotics] how much time single instruction takes?

Expand Messages
  • Brian Dean
    Nov 1, 2003
    • 0 Attachment
      On Fri, Oct 31, 2003 at 11:58:40PM -0500, David VanHorn wrote:

      > >As far as I know Atmel AVR is using Harvard
      > >Architecture, RISC and Pipelining to reach that speed.
      > >Could anybody explain more detail about this?
      >
      > I don't know that it's pipelined.

      I think you are right - this document says it is not:

      http://www.atmel.com/dyn/resources/prod_documents/atmelavr.PDF

      It says: "For all intents and purposes, the CPU has no pipeline. It
      retrieves both source operands, executes the instruction, and stores
      the result in a single clock cycle. Branch latency is one clock for
      taken branches. All operations are register-to-register; the chip
      follows a strinct load/store model."

      I recall hearing something similar at a recent Atmel seminar.

      Cheers,
      -Brian
      --
      Brian Dean, bsd@...
      BDMICRO - Maker of the MAVRIC ATmega128 Dev Board
      http://www.bdmicro.com/
    • Show all 19 messages in this topic