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15318Re: [SeattleRobotics] how much time single instruction takes?

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  • Brian Dean
    Nov 1, 2003
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      On Fri, Oct 31, 2003 at 11:58:40PM -0500, David VanHorn wrote:

      > >As far as I know Atmel AVR is using Harvard
      > >Architecture, RISC and Pipelining to reach that speed.
      > >Could anybody explain more detail about this?
      > I don't know that it's pipelined.

      I think you are right - this document says it is not:


      It says: "For all intents and purposes, the CPU has no pipeline. It
      retrieves both source operands, executes the instruction, and stores
      the result in a single clock cycle. Branch latency is one clock for
      taken branches. All operations are register-to-register; the chip
      follows a strinct load/store model."

      I recall hearing something similar at a recent Atmel seminar.

      Brian Dean, bsd@...
      BDMICRO - Maker of the MAVRIC ATmega128 Dev Board
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