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4Re: High enrolment

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  • rtstofer
    Aug 14, 2005
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      --- In STMicroSPEAr@yahoogroups.com, "Rick Collins" <gnuarm@a...>
      wrote:
      > I have started several ARM groups and this is the highest enrolment
      > for the first week I have ever seen. Most groups only reach this
      > level after a month or more.
      >
      > I see there are not many posts though. I guess with little SPEAR
      > information being available, it is hard to have a question or
      comment.
      >
      > How about telling us why you are interested in the SPEAR devices? Do
      > you have an application where the SPEAR would do the job better than
      > anything else?

      Maybe... Not having seen the datasheet it is hard to tell. I have
      been looking at maze solving robots. Specifically, I have been
      looking at implementing the flood-fill algorithm in a number of ways.
      At first I tried the Atmel ATmega128 and it can solve for a single
      cell in 7 mS. I moved to the Philips LPC2106 and it can solve a cell
      in 1.6 mS. I also tried a rather naive FPGA design and it can solve
      the entire 256 cells in a few microseconds. Unfortunately, my first
      cut at the cell design required something around 1,000,000 gates.

      Frankly, the LPC2106 is probably what I'll use unless I change to a
      similar chip with an A/D converter. I really like the development
      environment for the Olimex prototype board.

      The other possibility: I am looking at doing a hexapod robot with 18
      servos and perhaps another couple for tilt/pan for the ultrasonic
      detector.

      I have a servo controller that will handle 21 servos and it connects
      over the I2C bus. I can run this from either the ATmega128 or the
      LPC2106 but in either situation, the processor is heavily involved in
      the I2C transfer. I designed an FPGA solution that looked like a
      register file of 32 position registers. Now the processor can just
      jam the value into a 16 bit register in a memory mapped area. Right
      now it is just an idea because adding a 300k gate FPGA doesn't seem
      practical. I need to revisit the 32 down counters and get rid of the
      subtractors.

      This would be a slick application for a hybrid device but the CPU
      itself needs to be high performance. Like running the LPC2106 with a
      60MHz internal clock and executing one instruction per clock.

      Again, I have no information about the device but it seemed quite
      interesting. But, it is one thing to develop a CPU/FPGA, it is
      another to have a FREE toolchain: IDE, compiler, linker, debugger,
      VHDL/Verilog synthesizer, etc. And, without the FREE toolchain the
      device doesn't mean a lot to me. We'll see...
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