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Re: Memories AVR the way we were. (Update)

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  • ufo2joe
    To answer my own question and for the benefit of future readers regarding the accessing of SRAM within the AVR family. To read the Programs own Flash RAM or
    Message 1 of 5 , Apr 2, 2006
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      To answer my own question and for the benefit of future readers
      regarding the accessing of SRAM within the AVR family.

      To read the Programs own Flash RAM or EEPROM one needs to set a 2
      byte pointer and load the contects through it.

      The SRAM can be read directly with the OPCODE LDS (Load from SRAM)
      and STS (Store to SRAM) and not the register MOV instruction,
      however the first 32 bytes of the SRAM are actually the 32 working
      registers and mapped-in after than are the I/O ports, so the first
      usable SRAM location starts at $100 and goes to the End-of-SRAM
      (RAMEND) where most locate their stack.

      I hope futures readers of this post will find this information
      useful.

      --- In ORE_bits@yahoogroups.com, "stephane641" <stephane641@...>
      wrote:
      >
      > wow. I feel rusty.
      > I never really touched the assembly side of the AVR because I never
      > had to. I just know GCC does a good job of optimizing my code.
      >
      > From a quick browse of the mega8 data sheet it seems the RAM is
      mapped
      > after the registers so you can access it like any other register.
      >
      > The X,Y & Z pointer registers are only used in indirect memory
      > addressing modes. Direct mem access can access the whole data
      space.
      >
      > Accessing the FLASH is different and you then need the special
      SPM/LPM
      > instructions.
      >
      > This should be fairly well explained in the Data sheet's "AVR
      ATmegax
      > Memories" chapter.
      >
      > But coding assembly for a new architecture is always tough at
      first.
      > That's why I prefer C. It abstracts away the peculiarities of the
      > architecture.
      >
      > "Assembly" is a synonym for "pain" if you ask me. :)
      >
      > Have a good pain, ;)
      >
      >
      > --- In ORE_bits@yahoogroups.com, "ufo2joe" <ufo-joe@> wrote:
      > >
      > > From what I can gather so far from the Datasheets. To access a
      RAM
      > > location I need to load up a two byte pointer then load the
      > > information through the pointer. That just seemes like a lot of
      > > clocks just to use some RAM and I just don't think I'm reading
      > > things correctly because it would just slow things down way too
      much,
      > > which defeats the purpose of a RISC chip in the first place.
      > >
      > > I kow there are PIC users, does the PIC access RAM this way also?
      > >
      > > Thanks for the reply.
      > >
      > >
      > >
      > > --- In ORE_bits@yahoogroups.com, Albert den Haan
      > > <albert.denhaan@> wrote:
      > > >
      > > > ufo2joe:
      > > >
      > > > From my skims of the AVR documentation, the AVR's
      implementation
      > > of the
      > > > Harvard architecture has no RAM for a program to run out of.
      > > > http://en.wikipedia.org/wiki/Harvard_architecture
      > > >
      > > > In these embedded chips all program instructions are run out
      of
      > > flash
      > > > eeprom (or ROM) and it takes specific gymnastics to change the
      > > program
      > > > flash. Microchip PICs do the same thing. This makes sense
      when
      > > you
      > > > want the same program to run all the time, and want it to be
      hard
      > > to
      > > > corrupt that program.
      > > >
      > > > Microprocessors intended for general purpose reconfigurable
      > > computers
      > > > (such as the Intel x'86 and PowerPC family use a memory system
      > > that does
      > > > not make this distinction and thus make it easy to change
      program
      > > > storage on the fly. This is called a von Neumann
      > > > http://en.wikipedia.org/wiki/Von_Neumann_architecture, and it
      is
      > > what
      > > > most programmers are familiar with.
      > > >
      > > > For what it's worth Motorolla 68HC{11,12,912} chips (and Zilog
      > > chips?)
      > > > are von Neumann architectures and have a single memory address
      > > space and
      > > > can run programs out of RAM. In production systems the
      appropriate
      > > > portions of the memory space are replaced with ROM chips.
      > > >
      > > > Albert.
      > > >
      > > >
      > > >
      > > >
      > > > ufo2joe wrote:
      > > >
      > > > >I have a general question about the AVR micrcontrollers. I
      have
      > > been
      > > > >prouring over the data sheets and one thing still confuses me.
      > > > >Is there anyone here that might help me find the answer.
      > > > >
      > > > >I am very confused about the memory architecture. I
      understand
      > > that
      > > > >there are 32 registers that reside in the bottom of RAM and
      that
      > > > >Program Memory is Separate from Data Memory, bowever it
      appears
      > > that
      > > > >there is no internal RAM (other than the registers and
      Program
      > > RAM)
      > > > >that can be accessed directly. Is this correct?
      > > > >
      > > > >It appears that all such RAM access have to be done
      indirectly
      > > through
      > > > >memory pointers.
      > > > >
      > > > >Thank you very much.
      > > > >
      > > > >
      > > > >
      > > > >
      > > > >
      > > > >
      > > > >To unsubscribe from this group, send an email to:
      > > > >ORE_bits-unsubscribe@
      > > > >
      > > > >
      > > > >Yahoo! Groups Links
      > > > >
      > > > >
      > > > >
      > > > >
      > > > >
      > > > >
      > > > >
      > > >
      > >
      >
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