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675001 SDRAM refresh problem

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  • Ben Dooks
    I am having trouble with an Oki 675001 design and initialisaiton of an 16Mx16 SDRAM part. The problem seems to be that the Oki is not producing any REFRESH
    Message 1 of 2 , Jun 14, 2005
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      I am having trouble with an Oki 675001 design and initialisaiton
      of an 16Mx16 SDRAM part.

      The problem seems to be that the Oki is not producing any
      REFRESH accesses after initialisation, having programmed the
      registers as per section 11 (11.3.4).

      The SDRAM can be accesses for read/write, but without the
      refresh, the data degrades after a second or two, causing the
      system software to crash.

      I have checked the SDRAM CLK input is being fed with a signal
      (equal to the core clock) and the SDRAM CKE pin is being kept
      high to indicate the clock is meant to be active.

      Anyone got any helpful suggestions, or pointers to any more
      information on the subject. I have looked at several bits of
      example code, but none have been very much help.
    • kendwyer
      hi, this is snippet of the setup_sdram from the 5003 cd...this shows the sequence for setting up sdram. hope this help. thanks ken
      Message 2 of 2 , Jun 16, 2005
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        hi,

        this is snippet of the setup_sdram from the 5003 cd...this shows the
        sequence for setting up sdram. hope this help.
        thanks
        ken



        /********************************************************************
        ********/
        /* Setup of external
        DRAM */
        /* Function :
        setup_ext_dram */
        /*
        Parameters
        */
        /* Input :
        Nothing */
        /* Output :
        Nothing */
        /********************************************************************
        ********/
        void setup_ext_dram(void)
        {
        int i;

        /* wait 200us (for HCLK:33MHz) */
        /* DBWC has to be set more than 200us after power was turned on.
        */
        /* please modify loop counts to suit your system. */
        /* -- HCLK : 60MHz -- */
        /* 2414 = 1328 * (60/33) */
        /* 0x96E = */
        for(i=0; i<0x96E; i++)
        ;

        /* DRAM refresh cycle control register0,1
        (RFSH0@0x7818_0014,RFSH1@0x7818_001C) */
        /* refresh cycle = 64KHz * 1 = 64KHz */
        put_wvalue(RFSH0, RFSH0_SINGLE); /* magnification = 1 */
        put_wvalue(RFSH1, 0x0202); /* cycle = 64KHz */

        /* DRAM bus width control register (DBWC@0x7818_0000) */
        put_wvalue(DBWC, DBWC_DBDRAM16); /* bus width : 16bits */

        /* DRAM parameter control register (DRPC@0x7818_0008) */
        put_wvalue(DRPC, 0x9);

        /* all bank pre-charge */
        put_wvalue(DCMD, DCMD_S_PALL);

        /* CBR * 8 */
        for(i=0; i<8; i++)
        put_wvalue(DCMD, DCMD_S_REF);

        /* DRAM control register (DRMC@0x7818_0004) */
        put_wvalue(DRMC, DRMC_8bit|DRMC_SDRAM /* AMUX:8bit,
        ARCH:SDRAM, */
        |DRMC_2CLK|DRMC_PD_DIS /* prelat:2clock,
        PDWN:disable, */
        |DRMC_CBR_EXE); /* CBR:execute */

        /* SDRAM mode register (SDMD@0x7818_000C) */
        put_wvalue(SDMD, SDMD_CL2|SDMD_MODEWR); /* CL-2
        only when MODEWR bit
        is written as 1,
        mode setup is
        performed. */

        /* DRAM power down mode control register (PDWC@0x7818_0018) */
        put_wvalue(PDWC, PDWC_16); /* when 16 or more cycles of idol
        state continue,
        it shifts to power down mode.
        but automatic shifting to SDRAM
        power down mode
        is disable */

        return;
        }



        --- In OKI-ARM-mcus@yahoogroups.com, "Ben Dooks" <ben-yahoo@f...>
        wrote:
        > I am having trouble with an Oki 675001 design and initialisaiton
        > of an 16Mx16 SDRAM part.
        >
        > The problem seems to be that the Oki is not producing any
        > REFRESH accesses after initialisation, having programmed the
        > registers as per section 11 (11.3.4).
        >
        > The SDRAM can be accesses for read/write, but without the
        > refresh, the data degrades after a second or two, causing the
        > system software to crash.
        >
        > I have checked the SDRAM CLK input is being fed with a signal
        > (equal to the core clock) and the SDRAM CKE pin is being kept
        > high to indicate the clock is meant to be active.
        >
        > Anyone got any helpful suggestions, or pointers to any more
        > information on the subject. I have looked at several bits of
        > example code, but none have been very much help.
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