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142Re: Flushing the cache after turning it off

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  • kendwyer
    Feb 24, 2006

      Note the following: "Since the CPU will be made to wait until the
      cache memory initialization has been completed. The instruction
      of writing to the FLUSH register will take about 128 instruction cycles."

      If you can send me the test case I will see if I can repeat on my setup.


      --- In OKI-ARM-mcus@yahoogroups.com, "rsprowson" <news@...> wrote:
      > --- In OKI-ARM-mcus@yahoogroups.com, "kendwyer" <kendwyer@> wrote:
      > >
      > > Hi,
      > >
      > > Here is some code for doing the write back. Let me know if this
      > > helps...
      > [snip code]
      > > put_wvalue(FLUSH, FLUSH_FLUSH);
      > What's the rationale behind the write to the Flush register? I didn't
      > spot that in the datasheet. Or is it "belt & braces"?
      > Sadly, it doesn't seem to make a difference. The cache is still
      > turned off and looks like it is flushed, but with some undefined
      > behaviour (hard to put my finger on as it manifests itself in unusual
      > ways, but it's as though an ARM register got corrupted or maybe only
      > a partial flush occurred).
      > What happens if you run that test code using ROM during the flush
      > instead of the SRAM? ie.
      > zero fill SRAM
      > turn cache on
      > fill with non zero
      > flush using ROM during the LOAD operations
      > cache off
      > I think I found a repeatable test case for my board this morning so
      > might see if I can simplify it some more,
      > Sprow.
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