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140Re: Flushing the cache after turning it off

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  • kendwyer
    Feb 20, 2006
    • 0 Attachment
      Hi,

      Here is some code for doing the write back. Let me know if this helps...

      Thanks
      Ken

      /* constants */
      #define DRAM_BASE (0xC0000000) /* base address of external SDRAM */
      #define SRAM_BASE (0x50002000) /* base address of internal RAM */
      #define BYTE_2K (0x800) /* 2Kbyte size */
      #define BYTE_8K (0x2000) /* 8Kbyte size */


      /******************************************************************/
      /* Write Back test */
      /* Function : write_back */
      /* Parameters */
      /* Input : Nothing */
      /* Output : Nothing */
      /******************************************************************/
      void write_back()
      {
      UBYTE *address;

      /* Clean Internal-SRAM */
      for(address = (UBYTE*)SRAM_BASE;
      address<(UBYTE*)((void*)(SRAM_BASE+BYTE_8K)); address++){
      put_value(address, 0x00);
      }
      /* internal SRAM initialize */
      cache_on(CACHE_BANK10); /* SRAM BANK : Cache enable */
      /* Set 'F'data to Internal-SRAM */
      for(address = (UBYTE*)SRAM_BASE;
      address<(UBYTE*)((void*)(SRAM_BASE+BYTE_8K)); address++){
      put_value(address, 0xFF);
      }

      address = (UBYTE*)SRAM_BASE;
      put_wvalue(CON, CON_WAY0 | CON_LOAD | CON_LOCK0); /* Set Load
      mode to Way0 */
      sram_read((UWORD*)address); /* dummy data read (2Kbytes) */

      address = ((UBYTE*)SRAM_BASE + BYTE_2K);
      put_wvalue(CON, CON_WAY1 | CON_LOAD | CON_LOCK0); /* Set Load
      mode to Way1 */
      sram_read((UWORD*)address); /* dummy data read (2Kbytes) */

      address = ((UBYTE*)SRAM_BASE + (BYTE_2K * 2));
      put_wvalue(CON, CON_WAY2 | CON_LOAD | CON_LOCK0); /* Set Load
      mode to Way2 */
      sram_read((UWORD*)address); /* dummy data read (2Kbytes) */

      address = ((UBYTE*)SRAM_BASE + (BYTE_2K * 3));
      put_wvalue(CON, CON_WAY3 | CON_LOAD | CON_LOCK0); /* Set Load
      mode to Way3 */
      sram_read((UWORD*)address); /* dummy data read (2Kbytes) */

      put_wvalue(FLUSH, FLUSH_FLUSH);

      cache_off(CACHE_BANK10); /* SRAM BANK : Cache disable */

      return;
      }


      --- In OKI-ARM-mcus@yahoogroups.com, "rsprowson" <news@...> wrote:
      >
      > --- In OKI-ARM-mcus@yahoogroups.com, "kendwyer" <kendwyer@> wrote:
      > Hi,
      >
      > > > I'm noticing some slightly odd behaviour when turning the cache
      > > > off
      > > > which makes me suspicious that the details in the datasheet
      > > > suggesting how to flush the cache aren't quite right.
      > > >
      > > > Anyone here had problems/successes in this area?
      > > >
      > > > The sequence is
      > > > - power up processor, hence the cache is off
      > > > - enable the cache, everything runs fine
      > > > - disable the cache & flush
      > > > - random skipping to wrong address
      >
      > > In your description you mention that you "disable the cache &
      > > flush"...
      > >
      > > Do you diable and then flush or flush and then disable?
      >
      > Flush then disable, though I realise that might sound odd.
      > Essentially I used the description in 9.5.2 of the datasheet, and
      > without posting the actual assembler here I do:
      >
      > Push non ATPCS preserved registers
      > Disable I and F in the CPSR
      > Get the address of a block of ROM which doesn't contain code
      > Align the address onto an 8k boundary
      > for (WAY=0; WAY<4; WAY++)
      > {
      > Lock WAY
      > Read the 2k into the locked WAY
      > }
      > Write 0 into the CACHE register
      >
      > > Do you do a "write back" before the flush?
      >
      > Yes, as long as the above worked, which is where my suspicion lies.
      >
      > > What memory areas are cacheable?
      >
      > Bank 0 and 25 (SDRAM and ROM respectively).
      >
      > > If you do not perform a writeback then there may be cache coherency
      > > issues. Also ensure that the cache is correctly initialized:
      > >
      > > void init_cache(void)
      > > {
      > > put_wvalue(CACHE, 0);
      > > put_wvalue(CON, 0);
      > > put_wvalue(FLUSH, 0x1);
      > >
      > > return;
      > > }
      >
      > Yup, already doing that, albeit in assembler.
      > Perhaps reading the 8k from a cached area is upsetting things, but I
      > can't think why?
      >
      > It's doing /something/ as there are a couple of places where I need
      > to be sure the value makes it back into SDRAM (incase someone resets
      > the ARM at just that moment), without the flush those bits fail after
      > a reset, with the flush they work as I anticipated.
      > Sprow.
      >
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