Hi Jiri, Thank you for the comment. I am looking at mmu_xcache.vhd for reference. It seems 'dco.hit' signal indicates the cache hit event. Am I correct? Cheolchouoo@gmail.com
It indicates the number of clocks the pipeline is held due to an icache miss. Jiri ... From: "chouoo@... [LEON_SPARC]" Date:jiri_gaisler
Greetings all, I am questing this because I am curious to that what the "instruction cache hold" event name stands for in L3STAT module in grlib? The firstname.lastname@example.org
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