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a-160/161 question

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  • Peter Sedin
    At muff wiggler I read that the clock pulses does not reset the divisions after reset.. like in the picture.. why not??? Mvh Peter H.K Sedin [Non-text portions
    Message 1 of 3 , May 2, 2013
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      At muff wiggler I read that the clock pulses does not reset the divisions
      after reset..
      like in the picture.. why not???


      Mvh

      Peter H.K Sedin


      [Non-text portions of this message have been removed]
    • ddoepfer
      Not the clock signal but the reset signal triggers the reset, i.e. a positive voltage (not the rising slope !) at the reset input resets all A-160 outputs to
      Message 2 of 3 , May 3, 2013
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        Not the clock signal but the reset signal triggers the reset, i.e. a
        positive voltage (not the rising slope !) at the reset input resets all
        A-160 outputs to zero and A-161 to step 1. The reset is static, i.e. as long
        as the reset signal is high all A-160 outputs remain low and A-161 stays at
        step 1 (even if clock pulses are present). Clock and reset are independent
        from each other for A-160/A-161 combo (in contrast to the A-154 where a
        reset signal triggers kind of a "wait state" and the actual reset is carried
        out at the next clock pulse that follows the reset).

        Best wishes
        Dieter Doepfer


        > -----Ursprungliche Nachricht-----
        > Von: Doepfer_a100@yahoogroups.com
        > [mailto:Doepfer_a100@yahoogroups.com]Im Auftrag von Peter Sedin
        > Gesendet: Freitag, 3. Mai 2013 08:09
        > An: doepfer_a100
        > Betreff: [Doepfer_a100] a-160/161 question
        >
        >
        > At muff wiggler I read that the clock pulses does not reset the divisions
        after reset.
        > like in the picture.. why not???
        >
        >
        > Mvh
        >
        > Peter H.K Sedin
      • Peter Sedin
        thanks Dieter! 2013/5/3 ... -- Mvh Peter H.K Sedin [Non-text portions of this message have been removed]
        Message 3 of 3 , May 3, 2013
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          thanks Dieter!


          2013/5/3 <yahoo@...>

          > **
          >
          >
          > Not the clock signal but the reset signal triggers the reset, i.e. a
          > positive voltage (not the rising slope !) at the reset input resets all
          > A-160 outputs to zero and A-161 to step 1. The reset is static, i.e. as
          > long
          > as the reset signal is high all A-160 outputs remain low and A-161 stays at
          > step 1 (even if clock pulses are present). Clock and reset are independent
          > from each other for A-160/A-161 combo (in contrast to the A-154 where a
          > reset signal triggers kind of a "wait state" and the actual reset is
          > carried
          > out at the next clock pulse that follows the reset).
          >
          > Best wishes
          > Dieter Doepfer
          >
          > > -----Ursprungliche Nachricht-----
          > > Von: Doepfer_a100@yahoogroups.com
          > > [mailto:Doepfer_a100@yahoogroups.com]Im Auftrag von Peter Sedin
          > > Gesendet: Freitag, 3. Mai 2013 08:09
          > > An: doepfer_a100
          > > Betreff: [Doepfer_a100] a-160/161 question
          >
          > >
          > >
          > > At muff wiggler I read that the clock pulses does not reset the divisions
          > after reset.
          > > like in the picture.. why not???
          > >
          > >
          > > Mvh
          > >
          > > Peter H.K Sedin
          >
          >
          >



          --


          Mvh

          Peter H.K Sedin


          [Non-text portions of this message have been removed]
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