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Arm Developer Studio

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  • Nigel Brown
    Is anyone using this to develop for the ADuC7xx? If so do they have any example projects they fancy sharing?
    Message 1 of 4 , Apr 27, 2007
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      Is anyone using this to develop for the ADuC7xx? If so do they have
      any example projects they fancy sharing?
    • Steve Franks
      Never heard of it. I m having good luck with gnuarm (gcc). Just got my first ADuC in hand last week. I use scite for an editor - with a few tweaks, it will
      Message 2 of 4 , Apr 27, 2007
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        Never heard of it.  I'm having good luck with gnuarm (gcc).  Just got my first ADuC in hand last week.  I use scite for an editor - with a few tweaks, it will clean, make, and program the device with lpc21isp.  Even with the WinARM gcc distrubution, I've still had to do quite alot of tweaking to get things going from the examples ( i.e. newlib/stdio, g++, etc.) - happy to share if you go the gcc/gnuarm/yagarto/winarm/rowley/keilgcc route.

        Steve

        On 4/27/07, Nigel Brown < nigelibrown@...> wrote:

        Is anyone using this to develop for the ADuC7xx? If so do they have
        any example projects they fancy sharing?




        --
        Steve Franks, KE7BTE
        Staff Engineer
        La Palma Devices, LLC
        http://www.lapalmadevices.com
        (520) 312-0089
      • paloalgodon
        We are attempting to use the SPI on the ADuC7024; An arbitrary pin is used for the chip select signal, but the timing is off: the chip select rises before the
        Message 3 of 4 , May 31, 2007
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          We are attempting to use the SPI on the ADuC7024; An arbitrary pin is
          used for the chip select signal, but the timing is off: the chip
          select rises before the 8 bits have been clocked out. Are bits 0 and
          1 in the SPISTA register guaranteed to be synchronous to the transfer?
          We are using those bits to control the chip select. Interrupts are
          disabled. There is only one device on the bus with the 7024, and it
          is a deidcated slave, so it cannot be driving the chip select, SCK, or
          MOSI pins.

          Signal levels and such look good on the scope now, althought the
          MISO/MOSI were only 2 volts (not 3.3) before we set the GP1DAT and
          GP1PAR registers, which the datasheet would have one believe are
          unneccessary.

          code:

          //setup
          GP1CON &= ~(0x03330000UL);
          GP1CON |= 0x02220000UL;
          GP1DAT |= 0x50000000UL;
          GP1DAT &= ~(0x20000000UL);
          GP1PAR |= 0x01110000UL;
          SPIDIV = 31; SPICON = 0x004B;
          //xfer
          GP4DAT &= ~(1UL << (16 + 0));
          SPITX = txd;
          while (0x02 != (SPISTA & 0x02)) { }
          GP4DAT |= 1UL << (16 + 0);

          I see the chip select rise around bit 4, not bit 8. Worse, since I'm
          doing a multi-byte transfer, it's probably overflowing the SPITX
          register.

          Anyone else seen this?

          Steve
        • s_cornel_99
          The definition of bit 1 (0x02)says that it will trigger on either of two occurrences: SPITX Data Register IRQ. Set automatically if Bit 0 is clear or Bit 2 is
          Message 4 of 4 , Jun 6, 2007
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            The definition of bit 1 (0x02)says that it will trigger on either of
            two occurrences:
            "SPITX Data Register IRQ. Set automatically if Bit 0 is clear or
            Bit 2 is set. Cleared by writing in the SPITX register or if
            finished transmission disabling the SPI."

            I'm guessing that the underflow (b2) is tripping, while the empty
            status (b0) is not because the shifter is not empty.

            Try checking the empty status before you release the chip select.

            Steve

            --- In ADuC_ARM@yahoogroups.com, "paloalgodon" <stevefranks@...> wrote:
            >
            > We are attempting to use the SPI on the ADuC7024; An arbitrary pin is
            > used for the chip select signal, but the timing is off: the chip
            > select rises before the 8 bits have been clocked out. Are bits 0 and
            > 1 in the SPISTA register guaranteed to be synchronous to the transfer?
            > We are using those bits to control the chip select. Interrupts are
            > disabled. There is only one device on the bus with the 7024, and it
            > is a deidcated slave, so it cannot be driving the chip select, SCK, or
            > MOSI pins.
            >
            > Signal levels and such look good on the scope now, althought the
            > MISO/MOSI were only 2 volts (not 3.3) before we set the GP1DAT and
            > GP1PAR registers, which the datasheet would have one believe are
            > unneccessary.
            >
            > code:
            >
            > //setup
            > GP1CON &= ~(0x03330000UL);
            > GP1CON |= 0x02220000UL;
            > GP1DAT |= 0x50000000UL;
            > GP1DAT &= ~(0x20000000UL);
            > GP1PAR |= 0x01110000UL;
            > SPIDIV = 31; SPICON = 0x004B;
            > //xfer
            > GP4DAT &= ~(1UL << (16 + 0));
            > SPITX = txd;
            > while (0x02 != (SPISTA & 0x02)) { }
            > GP4DAT |= 1UL << (16 + 0);
            >
            > I see the chip select rise around bit 4, not bit 8. Worse, since I'm
            > doing a multi-byte transfer, it's probably overflowing the SPITX
            > register.
            >
            > Anyone else seen this?
            >
            > Steve
            >
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