At 03:56 PM 4/28/2008, you wrote:
I guess RT2
http://www.lekstutis.com/Artie/Ham/Projects/RT2.html) aims that. Is
problem using an FPGA in this way ? Because it is quite straightforward.
I mean something
similar to softrock, but instead of clocking logic, use an FPGA in a DDS
style (without lookup
and DAC) and use FPGA output to enable bus switches.
That technique will have considerable jitter, just adding a count to the
register and using bits from the counter for the clock, the accuracy
needed in the counters is quite high including lots of fractional bits
before the jitter is tamed enough. But even that will do only so much,
you need the clock to be as high as the logic can go, the higher the
clock the better it will perform. A 1 GHz clock will give you 1 ns
resolution hardly good enough. The SI570 uses a combination of variable
clock and a Fractional divider to give you both good frequency resolution
and clean output, but with a fixed FPGA clock you can't have
The reason a DDS works quite well is that the counter is way bigger than
the D/A and it provides for fractional outputs, the output filter also
helps get rid of some of the noise by interpolating in-between values.
DDS's have their own problems, lack of D/A resolution, unequal bit sizes,
and feed through noise tend to make spurs appear.
You will most likely be way better off by having the FPGA control the
SI570 for the LO generation, and let the FPGA do the signal
"Blessed are the cracked, for they shall let in the