... I ve been doing some investigation on the net because I m quite keen on such number crunchers but have been put off by the expense. Like dope pedlars, theMessage 1 of 22 , Aug 1, 2005View SourceOn Mon, 2005-08-01 at 20:44, elevensmooth wrote:
> --- In firstname.lastname@example.org, "Ron" <Yaho6Hb3c@s...> wrote:I've been doing some investigation on the net because I'm quite keen on
> > Perhaps when I get my design completed I can hook the development
> > board up to the Internet so that anyone can use it remotely. :-)
> OOOhhh! That's interesting. I'd been thinking that I'd need to
> purchase a system and run it myself. The issues I was mulling were a
> cost outlay and the difficulty of keeping the FPGA busy enough to
> justify the expenditure. But if my only cost is the coordination
> effort, it becomes interesting even if I only have a small amount of
> work. And if it turns out I have a large amount of work, then the
> purchase option would still be available.
such number crunchers but have been put off by the expense.
Like dope pedlars, the hardware manufacturers give out (almost) free
samples to get their customers hooked but charge real money for a long
term relationship. In particular, the software costs serious bucks even
though quite a lot of development hardware is available for a couple
hundred or less.
If there is a way of amortizing the software costs over a number of
fielded systems, I'd be *much* more interested in joining in and
contributing to others' efforts. That said, my extremely limited
hardware design experience dates from the early 80s when it was very
much 7400 TTL, PROMS, AMD 2900 series bit slices and the earliest PLA
implementations. I've a steep learning curve to climb.
... Yep, and I finally shelled out $500 for Lattice s full ispLever development software simply so that I could synthesise (ie; implement designs for) theMessage 2 of 22 , Aug 1, 2005View Source--- In email@example.com, Paul Leyland <pcl@w...> wrote:
> On Mon, 2005-08-01 at 20:44, elevensmooth wrote:Yep, and I finally shelled out $500 for Lattice's full ispLever
> Like dope pedlars, the hardware manufacturers give out (almost) free
> samples to get their customers hooked but charge real money for a long
> term relationship. In particular, the software costs serious
> bucks even though quite a lot of development hardware is
> available for a couple hundred or less.
development software simply so that I could synthesise (ie; implement
designs for) the high-end expensive Lattice FPGAs. The ispLever tools
(both the free and pay versions) can *only* be used to synthesize
designs for Lattice FPGAs, so it seems bizarre to me that Lattice
should be charging for the software. Seems like they should be giving
it away for free and encouraging as many people as possible to use
it!? Even so, the Lattice software tools are only about half the cost
of similar tools from Altera and Xilinx.
> If there is a way of amortizing the software costs over a number ofNot sure what you mean by this, but there is an option for a
> fielded systems, I'd be *much* more interested in joining in and
> contributing to others' efforts.
"floating" license. It's mostly used within companies but I see no
reason a group of people located anywhere couldn't do the same thing
as long as everyone has Internet access. The way it works is that only
one person can have the license "checked-out" at any given time, and
the Lattice license server verifies this as the key is checked in and
out by different users.
> That said, my extremely limitedDon't worry about it Paul. I designed my very first VLSI
> hardware design experience dates from the early 80s when it was very
> much 7400 TTL, PROMS, AMD 2900 series bit slices and the earliest PLA
> implementations. I've a steep learning curve to climb.
implementation of a Linear Iterative Array Multiplier/Adder (the one I
mentioned earlier that's described in Knuth) in 1983 by writing
a Pascal program to draw a plot of the different layers of the VLSI
traces I wanted in different colors. You would make a transistor by
crossing a plot line representing silicon over a different colored
plot line representing (I think) silicon dioxide. It took me several
evenings and weekends (it was a one day a week class lasting six weeks
that I took at my place of employment) to complete the literally
graphical design using Pascal. Whenever I start complaining about
Verilog I think back to those days. ;-) I never pursued VLSI design
after that, but some 26 years later I was able to produce functionally
the same circuit in Verilog in a single afternoon! Some higher level
languages (SystemC for one) are on the horizon, but so far the
software vendors charge an arm and leg for their software. There are
Open Source efforts at software design tools - and indeed I use the
totally free Icarus simulator to debug my own design - but the
"higher-level" design tools like Open SystemC are mostly in the "Beta"
or pre-release stages.
Anyhow I think hardware design in Verilog is kind of fun, albeit very
tedious. Now that I only have a couple more modules to debug it's
starting to get more exciting for me. I even ordered a LFEC20E-L-EV
LatticeEC20 Standard Evaluation Board for $175 from Lattice - less
than half the cost of the software I purchased from them! As you said,
software costs more than hardware in many cases. The LFEC20E is one of
their larger FPGA's but is still very affordable. I hope that it will
be large enough to actually implement a useful design with.
Actually I was just thinking more in terms of a simple ASCII text command line type interface. Ethernet interface IP designs are (I believe) freelyMessage 3 of 22 , Aug 1, 2005View SourceActually I was just thinking more in terms of a simple ASCII text
command line type interface. Ethernet interface "IP" designs are (I
believe) freely available, so the only work I would have to do is
implement a simple ASCII command line interpreter that accepts an
input (the number to be factored) and then spits a factor over the
same port just as if it were talking over a TTY port. All it would
do) to connect an ethernet virtual socket to a virtual ethernet socket
on the FPGA. Hopefully all the ethernet level protocol is part of the
free ethernet interface design so that the FPGA would only have to
worry about reading and writing data. That's the nice thing about
FPGAs or hardware design in general - it can do everything truly in
parallel without time slicing like computer operating systems do. Not
sure what I'd do about collisions if more than one user were trying to
access the device, but I could probably have it put out a busy message
of some sort when it's busy calculating. It would be nice to at least
implement Telnet, but I'm sure that would be too much of a burden for
Hi Folks, Consider this just a quick note to announce that tonight for the first time ever I HAVE SUCCESSFULLY TESTED MY VERILOG ECM DESIGN!!! It will beMessage 4 of 22 , Sep 16, 2005View SourceHi Folks,
Consider this just a quick note to announce that tonight for the
first time ever I HAVE SUCCESSFULLY TESTED MY VERILOG ECM DESIGN!!!
It will be awhile before I have any hard statistics on how wide the
data bus can be versus type of FPGA because there are an enormous
number of choices of FPGAs, and quite a bit of "clean-up" work and
testing remaining to be done, but initially at least the stats
probably won't be very impressive. Most likely the maximum size
composite it will be able to factor will be between 2^64 and 2^128 as
Anyhow, for the first time in many years I feel like opening a bottle
of some very old Cognac. :-)